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外文翻译及原文翻译 26168字 投稿:曾凂凃
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咨询应用工程师- 33关于直接数字频率合成器的问题作者
Eva Murphy [eva.]Colm Slattery [colm.] 什么是直接数字频率合成器?直接数字频率合成器(DDS)是一种产生模拟波形(通常是正弦波)的仪器,这种仪器是生成一个数字形式的时变信号,然后执行数字到模拟的转换。因为用一个DDS设备操作主要是数字形式,所以它可以提供输出频率之间的快速转换,较高的频率分辨率并且可以在一个宽频带上进行操作。随着设计和工艺技术的进步,现在的DDS器件都非常小巧,在低功率下也可以工作。为什么我们要使用直接数字频率合成器(DDS)?难道就没有其他产生频率的简单方法吗?能够准确地产生和控制各种频率和轮廓的波形的能力已成为一个通用于多个行业重要要求。在通信系统中能否利用良好的杂散性提供低相位噪声可变频率的活跃来源,或仅产生用于工业或生物医学测试设备的应用的频率刺激,便利、简洁和低成本是重要的设计考虑因素。频率产生的多种可能性对设计师来说是开放的,从锁相回路(PLL)——极高频率合成的基础技术,到以数模转换器(DAC)的动态编制程序输出来产生低频任意波形。但是DDS技术迅速在解决频率(或波形)产生的通信和工业应用要求上得到接受,因为单芯片集成电路器件可以简单的产生可编程模拟输出波形,具有较高的分辨率和精度。此外,在这两种工艺技术和设计的不断改进也使得成本和功耗较从前降低了许多。例如,AD9833——基于DDS的可编程波形发生器(图1)在5.5 V的电压下工作工作具有25 MHz的时钟,消耗的最大功率为30毫瓦。 图1
单片波形发生器 使用直接数字频率合成器(DDS)的主要优点有哪些?像AD9833 之类的DDS器件都可通过一个高速串行外设接口(SPI)进行编程,并且只需要一个外部时钟来生成简单的正弦波。 DDS器件,现已能产生频率从不到1赫兹到高达400兆赫(以1GHz的时钟为准)。其低功耗,低成本,单一小包装,固有的优良性能和能对输出波形的进行数字编程(和重新计划)的能力相结合的特点使DDS器件成为非常吸引人的解决方案,比包括离散元素的聚合的不太灵活的解决方案更好。哪种输出才能生成一个典型的DDS的设备?DDS器件不仅限于单纯的正弦波输出。图2显示了由AD9833产生的方、三角和正弦输出。 图2
DDS的方波、三角波、正弦波输出 DDS的设备如何产生正弦波?下面是一个DDS器件的内部电路故障:其主要组成是相位累加器,相幅转换方法(通常是通过正弦查找表)和一个数模转换器。这些区块入图3所示。 图3
直接数字频率合成器组成框图 直接数字频率合成器产生一个给定频率的正弦波。频率取决于两个变量,参考时钟频率和编入频率寄存器的二进制数(控制字)。频率寄存器中的二进制数提供了相位累加器的主要输入。在使用正弦查找表时,相位累加器为查找表计算相位(角)的地址,它输出相角的正弦相应的幅度数字值至数字模拟转换器。反过来数字模拟转换器将这个数字转换为模拟电压或电流的相应值。要生成一个固定频率的正弦波,需要给每个时钟周期的相位累加器一个定值(相位增量决定于二进制数)。如果相位增量很大,相位累加器会加速正弦查找表过程,从而产生一个高频率的正弦波。如果相位增量很小,相位累加器将进行更多的步骤,因此产生波形较慢。一个完整的数字模拟转换器是什么意思?对所
将D / A转换器和DDS集成到一个芯片上称为一个完整的DDS解决方案,有 DDS器件均通用。让我们进一步谈一谈相位累加器。它是如何工作的?连续时间正弦信号具有0至2重复的固定相值范围。数字实现过程相同。计数器携带的功能允许相位累加器在DDS过程作为一个相轮。要理解这个基本功能,我们将正弦波振荡设想为一个绕圆圈旋转的矢量(见图4)。相轮上的指定点对应正弦波的等效点。由于矢量左右相轮转动,设想该角的正弦值产生相应的输出正弦波。矢量以恒定的速度围绕相轮的一个循环,形成一个输出正弦波的完整周期。相位累加器提供随相轮线性转动向量的等距相位角值。相位累加器的内容对应于输出正弦波循环的主要点。
数字相轮 相位累加器实际上是一个模- M的计数器,存储数量增加一次,接收一次时钟脉冲。递增量级是由二进制输入编码字决定(M)。这个字在参考时钟更新之间形成相位步长,有效地设置需要跳过的相轮点的数量。阶跃越大,相位累加器溢出越快并能完成与之等效的一个正弦波周期。相轮上的离散点的数量是由相位累加器(N)的分辨率决定,这也就决定了直接数字频率合成器的调谐分辨率。对于n = 28位,M值为0000 ... 0001的相位累加器,将使228个参考时钟周期(增量)后的增量溢出相位累加器。如果M值改为0111 ... 1111,相位累加器只在2个参考时钟周期后溢出(奈奎斯特定理要求的最低限度)。此关系是在直接数字频率合成器结构的基本方程中发现的: 其中:fOUT= 直接数字频率合成器的输出频率M =二进制谐调字fc=内部参考时钟频率(系统时钟)n=每组相位累加器的长度,用位量度M值的变化引起输出频率直接和相位连续的变化。锁相环中无环路建立时间。由于输出频率的增加,每个周期的样本数量减少。由于采样定律决定了每个周期至少有两次采样才能重建输出波形,最大的DDS输出频率为FC/ 2。然而实际应用中,为了提高重建波形的质量并对输出进行滤波,输出频率一般小于FC/ 2。当频率恒定时,相位累加器的输出呈线性增加,所以它产生的模拟波形是一个斜坡。那么线性输出如何转换成正弦波呢?一个幅相查找表用于转换相位累加器的瞬时输出值(28 AD9833位)它将正弦波的振幅信息,传给(10位)的D / A转换器。 DDS的组成充分利用正弦波的对称性和映射逻辑将累加器中四分之一的正弦波合成为一个完整的正弦波。相幅查找表通过通过从前向后浏览查找表的产生剩余数据。这个过程形象地呈现在图5中。 图5
信号在DDS系统中的流经途径 DDS的普遍用途是什么?目前使用的基于DDS的波形发生器的应用程序主要为以下两种主要类型:通讯系统设计人员需要活跃(即立即响应)的具有好的相位噪声性能的频率资源并且低杂散频率源往往选择其光谱性能和频率调谐分辨率相结合的DDS 。这些应用包括用DDS进行调制、作为参考锁相环来提高整体频率可调性,作为本地振荡器(LO),甚至可以作为直接的射频传输。另外,许多工业和医学领域将DDS作为一个可编程的波形发生器。因为DDS是数字可编程的,波形的相位和频率可以很容易调整,而不像传统的模拟程控波形发生器需改变外部元件。 DDS在实时控制时允许简单的频率调整来定位谐振的频率或补偿温度漂移。这些应用包括在可调频率源中使用DDS来测量阻抗(例如在基于阻抗的传感器中),为微刺激产制造脉冲波调制信号或检查局域网或***电缆中是否有衰减。
你认为对于设备和系统的设计者们DDS的关键优势是什么?高性能、功能集成的DDS芯片广泛应用在通讯系统和传感器领域。
当今成本低、他们吸引设计工程师的优势包括:o数字控制微赫兹的频率调整和副级逐步优化功能,o调整输出频率(或相位)的速度极快;相位连续频跳,无过冲/下冲或相关模拟的循环建立时间异常现象,oDDS的数字结构省去了手动调谐及由于元件老化和温度漂移对模拟合成器调整的需要,oDDS的结构有利于实现系统中数字控制接口远程控制并保证了在处理器的控制下的高分辨率。怎样使用DDS的设备进行频移键控(FSK)编码?二进制频移键控(通常简称为FSK)的是最简单的数据编码形式之一。通过将连续载波频率移到二分之一(此后均为二进制)离散频率来传输数据。频率F1(或许更高)为标志频率(二进制1),F0为空间频率(二进制0)。图6显示了标记空间数据和传输信号之间关系的例子。 图6
频移键控调制 这种编码方案用DDS很容易实现。代表输出频率的DDS频率控制字生成F0和F1,因为它们在0和1模式时进行传输。用户在传数据之前将两个调整字编入仪器。在AD9834的条件下,两个频率寄存器便于FSK编码。在设备上(FSELECT)的专用针接受调制信号并选择适当的控制字(或频率寄存器)。图7演示了的FSK编码的实现框图。 图7
基于DDS的频移键控编码器 PSK编码的实现过程又是如何呢?相移键控(PSK)是另一种数据编码的简单形式。在PSK过程中载波频率保持不变,通过传输信号的相位变化来传输信息。完成PSK的方法中,最简单的是二进制BPS码(BPSK),它仅需要两个信号相位:0度和180度。BPSK编码相移0为逻辑1输入,180为逻辑0输入。每个位的状态由前一位的状态决定。如果波相位不改变,信号状态保持不变(低或高)。如果波相位反转(180度的变化),那么信号状态变化(从低到高或从高向低)。PSK的编码用DDS芯片很容易实现。大多数的设备是单独的输入寄存器(相位寄存器),可以分别载入一个相位值。这个值直接添加到载波相位,不会改变其频率。通过改变该寄存器的内容来调变载波相位,从而产生PSK的输出信号。对于需要高速调制的应用,AD9834用专用切换输入引脚(PSELECT)来选择预载相位寄存器,这需要在寄存器和调控的载体之间选择。更复杂的PSK形式采用四或八个波阶段。这使二进制数据以每相变比BPSK调制更快的速度传播成为可能。在四相调制(正交PSK或QPSK)可能的相角为0、+90、每相移可以代表两个信号因子。-90和180度,AD9830,AD9831,AD9832和AD9835有四个相位寄存器,它们通过给寄存器持续更新不同的相位偏移来执行复杂的调制方案。多个DDS器件可以实现如智商能力的同步吗?用运行在相同主时钟上的两个单DDS器件输出两个可直接控制相位关系的信号是可以实现的。在图8中,两个AD9834使用一个参考时钟进行编程并用相同的复位引脚同时更新两个部分。使用这个装置可以实现IQ调制。 图8
多个DDS芯片的同步模式 置电和传输数据之前必须复位。这使得DDS输出已知相位,它作为共同的参照点实现多个DDS器件同步。当新的数据同时发送到多个DDS单元时,它可以使相位关系保持一致,并且它们的相对相移可以通过相移寄存器目的性的转移。 AD9833和AD9834的相位分辨率有12位,有效分辨率为0.1度。 [有关多个DDS单元同步详情请参阅应用笔记AN - 605。]基于DDS系统的主要性能指标是什么?相位噪声、抖动和无杂散动态范围(SFDR)。相位噪声是用来衡量振荡器的短期频率不稳定性(dBc / Hz)。据测定频率变化引起的单边带噪音在振荡器的工作频率下有两个或更多的频移(以下振荡器的工作频率在均为1 Hz)。这种测量方法已用在模拟通信行业的特殊应用上。DDS器件是否具有良好的相位噪声?采样系统中的噪音取决于许多因素。参考时钟抖动是DDS系统中的基本信号的相位噪声,相位截断可能引入错误的级别,这根据码字选择而定。对于完全由截断二进制编码字表示的比率是没有截断误差的。需要更多的比特率时,所产生的相位噪声截断误差表现在光谱图的尖峰上。他们的大小和分布取决于选择的代码字。DAC也会引入噪声。 DAC的量化或线性误差会产生噪声和谐波。图9显示了AD9834下DDS典型的相位噪声图。
AD9834的典型输出相位噪声曲线(输出频率为2 MHz,M的时钟是50兆赫) 什么是抖动呢?用均方根来衡量。一个完
抖动是数字信号边沿的动态位移偏离平衡位置的程度,美的振荡器的上升和下降沿时间是精确发生的,绝不会变化。这当然是不可能的,因为即使最好的振荡器也是由含有噪音源和其他干扰的实际部件组成的。高品质,低相位噪声的晶体振荡器在超过几百万时钟边沿积累下的抖动小于35皮秒(ps)。振荡器中的抖动由热噪声造成,振荡器中电子不稳定,外部干扰通过电源轨,地面,甚至输出进入系统。其他干扰包括外部磁场或电场如射频发射器附近的干扰,这将使抖动影响振荡器的输出。即使是一个简单的放大器、变频器或缓冲区都会引起抖动信号。因此一个DDS设备输出增加一定的抖动信号。由于每个时钟已经有抖动,选择一个低抖动振荡器是至关重要的开始。划分一个高频时钟频率是减少抖动的一种方法。随着频率的划分,相同数量的抖动发生的时间更长,这降低其在系统时间中的比例。为了减少抖动来源并避免引入额外的噪声,应该使用一个稳定的参
一般情况下,考时钟,避免使用信号和电路转换慢,使用频率最高的参考频率,以便增加采样。 无杂散动态范围(SFDR)是指最高基本信号和最高噪声信号的之间的比率(以分贝衡量),该信号包括频谱中最高的相关频率和谐波成分。要保证SFDR的值最合适必须用好的振荡器。在与其他通信通道和应用程序共享的频谱应用中SFDR是重要的性能指标。如果发送器的输出发送到其它频段就可能会损坏或中断邻近的信号。典型的主时钟为50- MHz的AD9834(10位DDS)输出如图10所示。在(a)图中,输出频率正好是1/3主时钟频率(MCLK)。由于频率的正确选择,25兆赫窗口下的频率无谐波,也称最小化,所有波峰信号都在80分贝以下(SFDR= 80分贝)。(b)中低频情况下波形含有更多的点(但对于理想波形并不足够,),并给出了一个更真实的图,第二个谐波频的最大冲击大约是50分贝(SFDR=50分贝)。 图10
输出的AD9834具有50 MHz的主时钟(a) fOUT = 16.667 MHz (i.e., MCLK/3); (b) fOUT = 4.8 MHz 你有更容易进行编程和预测DDS性能的工具吗?需要给定一个参考时钟和所需的输
在线互动设计工具是选择控制字的得力助手,出频率和/或相位。选择所需的频率,待外部滤波器重建后谐波和理想化输出。例如图11所示。表格数据也提供了主要的图像和谐波。 图11
屏幕演示互动式设计工具,一个sinx/ x的典型设备的输出图形 怎样利用这些工具对DDS进行编程?仅需要要求的频率输出和系统的参考时钟频率。该设计工具将输出全部程序。以图12为例,MCLK为25兆赫兹所需的输出频率为10兆赫兹。一旦启动按钮,完整程序的一部分就包含在初始化进程中。 图12
典型的编程序列演示 怎样评价DDS器件?所有已购买的DDS器件都有一个评估板。携带在专用软件中,用户在几分钟内就能进行测试/评估。每一个包含评估板的技术说明都有图示,并展示了最佳的电路板设计和布局。 Ask The Application Engineer—33All About Direct Digital SynthesisBy Eva Murphy [eva.]Colm Slattery [colm.] What is Direct Digital Synthesis?Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fne frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?The ability to accurately produce and control waveforms of various frequencies and profles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations.Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy. Furthermore, the continual improvements in both process technology and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.
What are the main benefts of using a DDS?DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefts of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extremely attractive solution—preferable to less-fexible solutions comprising aggregations of discrete elements. What kind of outputs can I generate with a typical DDS device?DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and sinusoidal outputs available from an AD9833.
How does a DDS device create a sine wave?Here’s a breakdown of the internal circuitry of a DDS device: its main components are a phase accumulator, a means of phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3. A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binary number programmed into the frequency register (tuning word).The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment—which is determined by the binary number) is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform. What do you mean by a complete DDS?The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI. Let’s talk some more about the phase accumulator. How does it work?Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2?. The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation.To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator provides the equallyspaced angular values accompanying the vector’s linear rotation around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the outputsine wave. The phase accumulator is actually a modulo-M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference- it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overfows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overfowing after 228 reference-clock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overfow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found inthe basic tuning equation for DDS architecture: where:fOUT = output frequency of the DDSM = binary tuning wordfC = internal reference clock frequency (system clock) n = length of the phaseaccumulator, in bitsChanges to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting fltering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave?A phase-to-amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value (28 bits for AD9833)—with unneeded less-signifcant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10-bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in
What are popular uses for DDS?Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring agile (i.e., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission.Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external components that would normally need to be changed when using traditional analog-programmed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift.Such applications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedance-basedsensor), to generate pulse-wave modulated signals formicro-actuation, or to examine attenuation in
LANs ortelephone cables.What do you consider to be the key advantages of DDS to design-ers of real-world equipment and systems?Today’s cost-competitive, high-performance, functionally integrated DDS ICs are becoming common in both communication systems and sensor applications. The advantages that make them attractive to design engineers include:o digitally controlled micro-hertz frequency-tuning and sub-degree phase-tuning capability, o extremely fast hopping speed in tuning output frequency (or phase); phase-continuous frequency hops with no overshoot/undershoot or analog-related loop settling-time anomalies,o the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions, ando the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control. How would I use a DDS device for FSK encoding?Binary frequency-shift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the mark-space data and the transmitted signal. This encoding scheme is easily implemented using a DDS. The DDS frequency tuning word, representing the output frequencies, is set to the appropriate values to generate f0and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the two required tuning words into the device before transmission. In the case of the AD9834, two frequency registers are available to facilitate convenient FSK encoding. A dedicated pin on the device (FSELECT) accepts the modulating signal and selects the appropriate tuning word (or frequency register). The block diagram in Figure 7 demonstrates a simpleimplementation of FSK encoding. And how about PSK coding?Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant and the phase of the transmitted signal is varied to convey the information.Of the schemes to accomplish PSK, the simplest-known as binary PSK (BPSK)—uses just two signal phases, 0 degrees and 180 degrees. BPSK encodes 0? phase shift for a logic 1 input and 180?
phase shift for a logic 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave reverses (changes by 180 degrees), then the signal state changes (from low to high, or from high to low).PSK encoding is easily implemented with DDS ICs. Most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, thus generating a PSK output signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase registers to be selected using a dedicated toggling input pin (PSELECT), which alternates between the registers and modulates the carrier as required.More sophisticated forms of PSK employ four- or eight- wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSKmodulation. In four-phase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, –90, and 180 each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers. Can multiple DDS devices be synchronized for, say, I-Q capability?It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin beingused to update both parts. Using this setup, it is possible to do I-Q modulation. A reset must be asserted after power-up and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the common reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phase-offset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of 0.1 degree.[For further details on synchronizing multiple DDS units please see Application Note AN-605.] What are the key performance specs of a DDS based system?Phase noise, jitter, and spurious-free dynamic range (SFDR). Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator. It is measured as the single-sideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1-Hz bandwidth) at two ormore frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog communications industry. Do DDS devices have good phase noise?Noise in a sampled system depends on many factors. Reference-clock jitter can be seen as phase noise on the fundamental signal in a DDS and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binary-coded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also contributes to noise in the system. DAC quantization or linearity errors will result in both noise and harmonics. Figure 9 shows a phase noise plot for a typical DDS device—in this case an AD9834. What about jitter?Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in degrees rms. A perfect oscillator would have rising and falling edges occurring at precisely regular moments in time and would never vary. This, of course,is impossible, as even the best oscillators are constructed from real components with sources of noise and other imperfections. A high-quality, low-phase-noise crystal oscillator will have jitter of less than 35 picoseconds (ps) of period jitter, accumulated over many millions of clock edges.Jitter in oscillators is caused by thermal noise, instabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. Other infuences include external magnetic or electric felds, such as RF interference from nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifer, inverter, or buffer will contribute jitter to a signal.Thus the output of a DDS device will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a high-frequency clock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time.In general, to reduce essential sources of jitter and avoid introducing additional sources, one should use a stable reference clock, avoid using signals and circuits that slew slowly, and use the highest feasible reference frequency to allow increased oversampling.Spurious-Free Dynamic Range (SFDR) refers to the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious, signal—including aliases and harmonically related frequency components—in the spectrum. For the very best SFDR, it is essential to begin with a high-quality oscillator.
SFDR is an important specifcation in an application where the frequency spectrum is being shared with other communication channels and applications. If a transmitter’s output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighboring signals.Typical output plots taken from an AD9834 (10-bit DDS) with a 50-MHz master clock are shown in Figure 10. In (a), the output frequency is exactly 1/3 of the master clock frequency (MCLK). Because of the judicious choice of frequencies, there are no harmonic frequencies in the 25-MHz window, aliases are minimized, and the spurious behavior appears excellent, with all spurs at least 80 dB below the signal (SFDR = 80 dB). The lower frequency setting in (b) has more points to shape the waveform (but not enough for a really clean waveform), and gives a mo the largest spur, at the second-harmonic frequency, is about 50 dB below the signal (SFDR = 50 dB).
Do you have tools that make it easier to program and predict the performance of the DDS?The on-line interactive design tool is an assistant for selecting tuning words, given a reference clock and desired output frequencies and/or phases. The required frequency is chosen, and idealized output harmonics are shown after an external reconstruction flter has been applied. An example is shown in Figure 11. Tabular data is also provided for themajor images and harmonics. How will these tools help me program the DDS?All that’s needed is the required frequency output and the system’s reference clock frequency. The design tool will output the full programming sequence required to program the part. In the example in Figure 12, the MCLK is set to 25 MHz and the desired output frequency is set to 10 MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register. How can I evaluate your DDS devices?All DDS devices have an evaluation board available for purchase. They come with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note accompanying each evaluation board contains schematic information and shows best recommended board-design and layout practice. 百度搜索“就爱阅读”,专业资料,生活学习,尽在就爱阅读网92to.com,您的在线图书馆!
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