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招联金融2016校园招聘
广东省深圳市
大型(1000人以上)
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2016招聘职位Company Jobs
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2016校园宣讲会AMD北京/上海校招社招职位内部推荐
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AMD北京/上海校招社招职位内部推荐
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AMD北京和上海，有想动一动的同学可以发简历到：
请注明北京还是上海。
上海的职位很多，范围很宽，竞争相对小一些。北京的职位相对少一些。
以下职位一般工作1-3年可申请Eng2, 3-5年Sr, 5年以上MTS。当然年限要求也不是非常严格。
北京职位：
Senior Layout Eng (Sr. PD)
Layout Eng (PD2)
Sr. Verification Eng (Sr. DV)
Sr. DFT Eng
上海职位：
MTS/ Sr. DV Engineer
MTS/ Sr. DFX Team Engineer
SMTS/MTS/ Sr. System Design Engineer
MTS/ Sr. GPU Firmware Engineer
Sr.Sys/Validation Engineer
SMTS/MTS/ Sr. System and Silicon Validation Lead(EAD)
MTS/ Sr.Graphic Board Design Engineer
Sr. PCB Layout Engineer
Sr. Memory Tuning Engineer
MTS/Sr. ASIC CAD Engineer
MTS/Sr. Integration Engineer
MTS/Sr. Physical Design Engineer
Physical Design Program Manager
MTS/Sr. ASIC Design Verification Engineer - GateSim
MTS/Sr. Performance Verification Engineer
MTS/Sr. GFX Design Verification Engineer
MTS/Sr. System Design Verification Engineer
MTS/Sr. Design Verification Engineer for Graphics Hardware
MTS/Sr. IP/SOC DV Engineer
MTS/Sr. Linux Gfx Driver
MTS/Sr. BIOS
MTS/Sr. Open GL
MTS/Sr. Windows D3D
D3D MTS/Sr
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
GPU Computer Architect(Performance Verfication)
More than 5 years’ experience with one of following:
- Software: OGL/D3D driver background
- 3D/GPU Architecture
- IC Design/verification Background
- CPU design/verification
- 3D Application programming etc.
- Compiler Back Ground
- Graphics Architecture
- GPGPU related jobs
Description of duties in addition to those in job description:
- Write test plan for new graphics chips
- Write performance tests for new graphics chips
- Debug/Analysis performance bugs of graphics chips
- Debug function bugs for performance tests
- Write performance analysis tools for new graphics chips
- Function verification for new features of graphics chips
- Write benchmarks for new graphics chips
- GPGPU performance verification
Preferred Experience:
- Master Degree or Above
- 5+ year experience on C\C++
- Plus with experience on CPU Design/Verification
- Plus with experience on Compiler
- Plus with 3+ years’ OpenGL/D3D programming experience
- Plus with 3+ years’ OpenGL/D3D driver experience
- Plus with 1+ years’ Linux/Shell
- Plus with 1+ years’ Perl/Python
- Familiar with Graphics Algorithm/Graphics Pipeline
- Proficient in English read/write/speaking/listening
- Good communication & Team worker
MTS ingineer for GPU integration
- Define GPU chip level specification, including clock and power targets, IP selection, floorplan review, package definition, PCB spec etc.
- Estimate GPU performance and TDP before ASIC bring-up. Provide regarding information to make up test plans.
- Communicate with design and marketing teams to define bounding-box for SKU volumn split.
- Bring-up ASIC. Guide hardware team to solve design problem in application. Help to short Time-To-Market.
Requirement:
- MS degree of EE with more than 5 years working experience in ASIC Company.&&
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Experience for ASIC tapout and bring up.
- Fluent English on talking, presentation and writing documents.&&
Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
Qualified candidate will perform some or all functions below:
- Participate in SOC full Chip DFT feature and architecture definition
- Responsible for DFT specification generation and review
- Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
- Perform verification on all DFT structures
- Generate DFT related timing constraints and work with PD team for timing closure
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE
- Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
-& &BS in EE & CS.&&MS preferred.
-& &MS +6 years, BS +8 years related experience
-& &Hands on working experience on ASIC DFT design and verification
-& &Familiar with entire ASIC design flow
-& &Experience with micro processor design a big plus
-& &Should have strong problem solving skills
-& &Good English hearing, speaking, reading and writing capabilities
-& &Good communication skills
Linux Graphics 2d driver
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Design, code, optimize and maintain AMD Linux graphics display driver
- AMD new graphics ASIC bring up under Linux
PREFERRED EXPERIENCE:
- Mater degree or above in C.S. or E.E.
- Good knowledge of C/C++ programming
- Good knowledge of Linux kernel programming
- Good knowledge of graphics is a plus
- Good written and verbal communication skills
- 3+ years experience in C/C++ programming
- 3+ years experience in Linux kernel development and debugging
- 3+ years experience in Linux device driver development and debugging
- Experience in graphics driver development is a plus
- Experience in XServer/X.Org development is a plus
- Fluent English language communication skills (including verbal/writing/reading), and CET-6 pass is a minimum
MTS ASIC CAD Engineer
- Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
- Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products
- Technical support and programming
- Interface with EDA venders on technology
Requirements:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
- Good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow
- Experience in ASIC design (digital design, Front-end and/or Back-end)
- Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route, signal integrity analysis, CTS design, design rule and connectivity verification, DFT ) and usage of related EDA tools
- Good written and spoken English
- Good communication skills and be able to work both independently and in a team
Highlight:
The key requirement is experience with UPF :
- UPF2.0 preferred but UPF1.0 is acceptable
- DC-T power aware synthesis
- MVRC checking on RTL used for synthesis and especially on netlist after&&synthesis
- Formality C both power aware with UPF and non-power aware
Hands on DFT implementation experience:
- DFT scan implementation using Mentor Testkompress (short term need) or Synopsys DFTMAx (long tern need)
- Understanding of scan compression logic generation and stitching of this logic into the design
- Understanding of Isolation wrappers for scan
Physical synthesis is nice to have:
- Physical synthesis C debugging synthesis with a floorplan, correlation of synthesis to physical layout (ICC placement)
MTS for ASIC Design Verification Engineer - GateSim
Description of job and responsibility:
- Understand the architecture of the chip and functional block being designed
- Build testbench and testcase for power-aware simulation
- Debug function/performance bugs of graphics chips
- Develop tools or monitors to improve verification
Requirement and Preferred Experience:
- Background in Electrical Engineering(EE) or Computer Science(CS) field
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with ASIC design or verification
- Understand low power design flow is a plus
- Experience on verilog HDL coding and debugging
- Experience on C/C++ programming and debugging(plus)
- Familiar with script(perl, tcl) program and makefile(plus)
- Familiar with SystemVerilog or SystemC (plus)
- Good written and fluent oral English
- Good communication skill and teamwork spirit
MTS GPU Firmware Development Engineer
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- A minimum of 6+ years experience on driver or embedded SW development and closely interact with HW designers (8+ years as a bachelor, 6+ years as a master)
- Hands on firmware or hardware driver development experience in an ASIC company is preferred
- Strong mix of large-scale software development ability and hardware understanding
- Proficient in C/C++ programming
- Familiar with Linux
- Hands-on experience with any one of display interface, PCI-E, and GDDR memories is preferred.
- Hands-on experience with 3D graphics is highly desired
- Strong experience with board bring up is essential
- Strong debugging and testing skills
- Strong communication skills
MTS PCB Layout Engineer
KEY RESPONSIBILITIES
- Work and communicate with layout teams in NA, architecture and execute AMD Client motherboards, graphics cards and server HST PCB layout design in SRDC
- Interface with NA technical staffs on the PCB layout related technical issues sync up,&&develop and deploy latest layout rules, execute new silicon layout trial routing
- Provide technical guidance to layout engineers in the team, ensure product requirements and design rules can be observed, mentor junior team members
- Identify program risks in terms of coverage, enablement and execution
- Collect training requirements and work out training plan to grow the PCB layout skills of the team
- Forward thinker to improve development process and drive PCB new technology innovation
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- 8+ years proven hands on experience in high speed PCB layout design for x86 PC motherboard, graphics and server products
- Prior experience in complex silicon bring up board design is highly desired
- Strong signal integrity (SI) and power integrity (PI) modeling experience is highly desired
- Skillful to operate Cadence Allegro, Concept, ProE along with strong skills in designing high speed, multi layer, high density designs, Analog/RF layout and power supply layout.
- Hands on experience to create and manage PCB library
- Highly self-motivated and a self starter and have good communications skills.&&
- Good knowledge of IPC specifications, PCB manufacturing and assembly process
- Excellent communication skills
Open GL MTS
DESCRIPTION OF DUTIES
- Implement OpenGL new features for new generation Graphic chips.
- Improve OpenGL benchmark performance.
- Work with key customers and vendors for implementation and issue solving.
- Interact with the Graphics Community .
Develop internal tools to improve development efficiency.
PREFERRED EXPERIENCE:
- Solid knowledge in C/C++ programming language, at least 5 years plus C/C++ language experience.
- Solid knowledge in Computer Graphics.
- Strong knowledge in Linux kernal, 1 year plus Linux development experience
- Strong knowledge in software development life cycle.
- Strong knowledge in debug tools usage.
- High quality team player as good team working spirits and easy going with team members.
- Prefer MS or higher education in CS or EE or Mathematic.
PD Program Manager
Job Description: The individual who fills this role will be responsible for driving programs from inception to full deployment. This individual will align all aspects of engineering and operation execution to meet business goals. This individual will interact with AMD executives and senior management team, 3rd-party partners, and possibly customers. This individual will be responsible for the management of program execution and its day-to-day activities centered around GPU development. This individual will work with engineering management to drive execution excellence, including key metrics like Time-to-Market, Time-to-Yield, and Silicon Quality Indicators. This individual will work collaboratively with the AMD Program Management community on infrastructure development and continuous process improvement. Work is strategic and tactical in nature with execution excellence being a key priority. Communication is a critical part of this role which includes interpreting/understanding business directions, explaining tactical details, and recommending solutions regarding complex program situations. Travel is expected for this role.
Job Requirements:
- Experience in managing complex, interrelated projects, programs, and functions to aggressive deadlines.
- Experience in ASIC development, including physical design.
- Experience in co-work with Physical Design manager for human resource plan according to global project schedule
- Experience in implement IT solution such as network, local disk, video conference, project share point maintenance.
- Experience in project schedule follow up and post project physical design review.
- Five years minimum related experience with two years (plus) management experience.
- BS in EE (or equivalent). Masters in EE or Engineering/Operations Management (or equivalent) preferred.
The ideal candidate will have experience with programs that can change quickly and may be speculative in nature. Candidate should be results driven, disciplined, and analytical. Candidate must exhibit very good problem solving skills, interpersonal skills, communications skills, and teamwork spirit.
SMTS - Elec. Analysis & Design(EAD)
JOB DESCRIPTION
Processor silicon interface functional and electrical validation engineer.&&In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management.
SKILLS REQUIRED
- BS-EE / BS-CE / Masters plus at least 5-8 years directly related experience. An advanced degree will be considered a plus.
- Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. Platform level electrical characterization experience with processor I/O interfaces is considered a plus.&&
- Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces
- Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications.
- Experience in software development including using languages such as Perl & Ruby to be used in silicon validation test plan development & execution
- Requires good written and oral communication skills.&&Demonstrate the ability to communicate with a variety of engineering disciplines and management.
SMTS - Graphics Board Design Engineer
KEY RESPONSIBILITIES
- Architecture the board design with best in class AMD GPU silicon, define the board design methodologies, design rules, technology roadmap
- Participate in silicon,&&board and system bring up
- Represent the team to participate in technical forum and the technical discussion on the design rules, technologies and industry specification (bus, memory, video interface, power etc)
- Understand marketing needs to ensure 'time to market' and quality and cost are balanced, maintain the technology advance and improve product competence&&
- Driving continuous improvement into existing board design and test methodologies
- Mentor junior design engineers
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English is required C verbal and written
EXPERIENCE AND SKILLS
- Bachelor or a Master of Science degree in Electrical Engineering, Computer Engineering or Computer Science
- A minimum of 10+ year hands on experience on graphics or CPU large scale silicon and board design
- Solid analog/digital mixed signal experience with silicon debug and lab tools
- Strong mix of high speed board design experience and software understanding
- Strong experience with silicon and board bring up is essential
- Strong debugging and testing skills
- PC system architecture knowledge
- Strong organization and planning skills
- Excellent communication skills
Sr&&Memory Tuning Engineer
KEY RESPONSIBILITIES
- Work with Manager, MTAG to support the qualification of memories on AMD graphics products.
- Develop and perform BIOS tuning and verify memory interface to test memories on various AMD boards.
- Qualify alternate memory sources for AMD OEM, ODM and AIB customers.
- Troubleshoot and provide solutions and perform FAs for problems related to functionality of memories on AMD boards.
- Perform Signal Integrity measurements as requested by OEM/ODM customers.
- Develop and improve memory test methodologies and procedures as the new memory technologies emerge.
- Assist in joint qualifications with memory suppliers for new die memories or new devices from new suppliers.
- Assist Field Application Engineers to support AMD customers in BIOS tuning and other memory related issues.
- Generate memory qualification reports and maintain memory AVLs.
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- At least 6+ years experience in electronic hardware development or test environment (6+ years as a bachelor, 4+ years as a master)
- Understand high-speed mix-signal multi-layer PCB design techniques
- Experience with DRAM memories and knowledge of different memory technologies is an asset.&&
- Skilful to operate high bandwidth oscilloscope for high speed signal measuring and analyzing
- Good communication skills and tact in order to set up liaison with customers and memory vendors and internal AMD departments.
- Knowledge of PC, CPU and graphics architectures
- Proven ability to effectively handle fast-pace projects
- Must be a self-motivated contributor and a strong team player
- Effective communication skills (both written and spoken) in English and Mandarin
Sr BIOS Design Engineer
PREFERRED EXPERIENCE:
- Bachelor degree or above in EE, CS, CE, with 5+ experience related to BIOS, firmware, or system software development.
- Strong Knowledge on ACPI, USB, PCIE, SATA and other PC industry standard
- Good at X86 assembly and C language
- Master at least one BIOS code base (Award, AMI, Insyde or Phoenix BIOS).
- Strong communication skills with both internal teams and customers
- UEFI experience is a big plus
Key responsibilities
- Design, develop, and debug BIOS (System Software) or UEFI Firmware for internal/external systems and platforms that use AMD CPU, AMD chipset, and 3rd party chipset.
- Be involved in day-to-day BIOS development work using PC assembly and C will need to interact with internal organizations, BIOS vendors, and customers.
- Comfortable working with PC hardware, platform, and
and the candidate must have strong system debugging skills. The following are typical tasks that the engineer will be responsible for:
- Design BIOS features required by AMD CPU
- Develop BIOS features for the new platforms designed in * Sustain existing BIOS; * Debug BIOS and s
- Assist CPU validation, platform validation, and debug engineers to develop/debug syste
- Provide consultation to internal and external customers regarding AMD features and programming requirements.
Sr. & MTS for System board deisgn
- Participates in discussions with Customers, Field Applications, Sales and Marketing to determine what hardware products are necessary to support and complement new silicon products.
- Develops and reviews comprehensive specifications for board-level and system-level products, based on a clear understanding of the function to be demonstrated across design, testing, and use of the product
- Designs board level products to meet the requirements of the project to agreed schedule, quality and cost requirements across the whole development lifecycle. Support outside manufacture venders.
- Focus on the electronic circuit design, test and debugging for the microprocessor based products such as PC desktop, mobile and server system.
- Responsible for board/system level development including schematics design, components selection, system bring-up, tuning, and functional validation and debugging.
- Develops FPGA firmware to support new board-level designs.
- Feedback and refine design rules with simulation and silicon design teams
- Negotiate solid solutions to technical issues and design challenges
- Ensure all processes are met in development
- Provides guidance for less experienced engineers
- Writes and reviews detailed technical documentation.
- Provides design assistance to Customers, Field Applications, and Sales.
- Supports resolution of customer problems which require system-level expertise.
PREFERRED EXPERIENCE:
- 5 + years experience in PC desktop, mobile or server system development or sustaining.
- Strong hardware design skills as measured by successful delivery of digital designs.
- Knowledge of design flow, product development processes, reliability verification, validation and compatibility testing.
- Experience in Microprocessor based motherboard designs in the PC Desktop, Mobile and Server markets.
- Familiar with PC, mobile or server architecture.
- Familiar with CAD Tools, including but not limited to OrCAD, Allegro, and Concept HDL.
- Familiar with Verilog, FPGA program and debug.
- Proficient with the Windows Operating System.
- Basic understanding of UNIX/Linux, software languages, and HDL sufficient to help debug system problems
- Bachelor or above degree in an Engineering or Science area.
- Ability to clearly communicate technical ideas across disciplines.
- Proficient English and Mandarin (listening, writing and speaking).
- Strong passion for achievement and career development.
- Self-motivated and able to work independently and effectively to meet time requirements.
Sr. ASIC Design Verification Engineer for Graphics Hardware
Job description:
- Understand the architecture of the chip and functional block being designed
- Build C/C++ model for simulation
- Build test bench and monitors for DUT
- Compose test plan and validation vectors to ensure functional completeness
- Debug function/performance bugs of graphics chips
Preferred Experience:
- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Should have excellent communication skills (both written and oral)
- Strong problem solving skills
Sr. SysTest Validation Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- To verify and validate hardware products designed and developed in house at AMD(ATI) using the standard qualification process developed within the hardware qualification group and participates in creating/improving all phases of test procedures and methodologies.
- Analyze the failures found in testing and support the internal design team to find the root
- Assist validation team in improving the validation methods and procedures.
- Executing and/or automating the tests including some signal integrity analysis.
- Communicate with various internal departments to resole anomalies
- Participate in issuing internal/external releasable test reports.
PREFERRED EXPERIENCE:
- Bachelor degree of electrical engineering/computer science/
- Good written and oral communication skills in both English and Chinese.
- Self-motivated and able to work independently and effectively to meet time requirements.
- Minimum 3-5 years of industrial experience in a hardware product testing or development environment
- Proficient in using electronic equipments such as digital oscilloscope, logic and network analyzer.
- Proficient in using all MS operating systems and the configuration/setting of PCs.
- Experienced in video/graphics product development and sustaining, system level hardware and software design
- Solid background in IC technology
- Experienced in board level design and development.
- Familiarity with Linux is an asset.
Staff Engineer of GFX Design Verification
Responsibility:
- Read and understand graphics specification for new hardware architecture.
- Work with NA team to write chip level test plan.
- Based on the test plan to write chip level tests to verify the function of graphics IP core.
- Debug the test to get expected result on C-model.
- Debug to locate issue of the fail on C-model and RTL-model, and push designer to fix.
Requirements:
- Master or above, major is CS, EE or Math.
- Strong program/debug ability on c/c++.
- 5 years or above experience on related task.
- Familiar to graphics algorithm like rendering/shader.
- Familiar to linux env/script is a big plus.
Staff IP-SOC DV Engineer
Job description:
- This candidate is responsible to lead a Design CAD team for Front-End ASIC Design and Verification.
- Understand the FE ASIC design flow, design verification flow, and integration flow.
- Consolidate the design and verification methodologies for graphics and micro-processor hardware.
- Develop infrastructure and release for variant IP/SOC teams.
- Explore the advanced design and verification methodologies for high efficient R&D.
- Also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment.
Preferred Experience:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Scripting language experience a plus (perl, ruby, tcl, etc.)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Should have excellent communication skills (both written and oral)
- Strong problem solving skills
Staff Physical Design Engineer
- PhD with 3+ years of industrial experience or MSEE with 6+ years of industrial experience in ASIC design
- 3+ years or more years of experience in physical design of deep submicron digital ASIC chips
- Hands on experience in large scale ASIC chip physical design
- Knowledgeable in all aspects of deep submicron ASIC design flow
- Successfully gone through several complete product development cycles
- Demonstrate leadership and work well with cross-functional teams
- Good listening, writing and speaking English
- Good communication skills, strong interpersonal skills and the flexibility
- Dedicated, hard working and good team player
- Familiar with Back-End (physical design) EDA tools
- Familiar with Front-End EDA tools is a plus
- Familiar with Unix/Linux environment and good at scripts
Staff System Design Verfication Engineer
- Have passion to learn new technology.
- strong skills in c++, systemc or verilog
- initiative, aggressive, and responsible
- Good at solving problem
-&&Good communication (both in Chinese and English) and team-work skills
- Good at self-learning
- Deep understanding about the verification methodology is an option
- Good understanding about memory virtualization or PCIE is an option
以下职位仅面向社会招聘，一般工作1-3年可申请Eng2, 3-5年Sr, 5年以上MTS。当然年限要求也不是非常严格。
上海职位：
MTS/ Sr. DV Engineer
MTS/ Sr. DFX Team Engineer
SMTS/MTS/ Sr. System Design Engineer
MTS/ Sr. GPU Firmware Engineer
Sr.Sys/Validation Engineer
SMTS/MTS/ Sr. System and Silicon Validation Lead(EAD)
MTS/ Sr.Graphic Board Design Engineer
Sr. PCB Layout Engineer
Sr. Memory Tuning Engineer
MTS/Sr. ASIC CAD Engineer
MTS/Sr. Integration Engineer
MTS/Sr. Physical Design Engineer
Physical Design Program Manager
MTS/Sr. ASIC Design Verification Engineer - GateSim
MTS/Sr. Performance Verification Engineer
MTS/Sr. GFX Design Verification Engineer
MTS/Sr. System Design Verification Engineer
MTS/Sr. Design Verification Engineer for Graphics Hardware
MTS/Sr. IP/SOC DV Engineer
MTS/Sr. Linux Gfx Driver
MTS/Sr. BIOS
MTS/Sr. Open GL
MTS/Sr. Windows D3D
D3D MTS/Sr
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
GPU Computer Architect(Performance Verfication)
More than 5 years’ experience with one of following:
- Software: OGL/D3D driver background
- 3D/GPU Architecture
- IC Design/verification Background
- CPU design/verification
- 3D Application programming etc.
- Compiler Back Ground
- Graphics Architecture
- GPGPU related jobs
Description of duties in addition to those in job description:
- Write test plan for new graphics chips
- Write performance tests for new graphics chips
- Debug/Analysis performance bugs of graphics chips
- Debug function bugs for performance tests
- Write performance analysis tools for new graphics chips
- Function verification for new features of graphics chips
- Write benchmarks for new graphics chips
- GPGPU performance verification
Preferred Experience:
- Master Degree or Above
- 5+ year experience on C\C++
- Plus with experience on CPU Design/Verification
- Plus with experience on Compiler
- Plus with 3+ years’ OpenGL/D3D programming experience
- Plus with 3+ years’ OpenGL/D3D driver experience
- Plus with 1+ years’ Linux/Shell
- Plus with 1+ years’ Perl/Python
- Familiar with Graphics Algorithm/Graphics Pipeline
- Proficient in English read/write/speaking/listening
- Good communication & Team worker
MTS ingineer for GPU integration
- Define GPU chip level specification, including clock and power targets, IP selection, floorplan review, package definition, PCB spec etc.
- Estimate GPU performance and TDP before ASIC bring-up. Provide regarding information to make up test plans.
- Communicate with design and marketing teams to define bounding-box for SKU volumn split.
- Bring-up ASIC. Guide hardware team to solve design problem in application. Help to short Time-To-Market.
Requirement:
- MS degree of EE with more than 5 years working experience in ASIC Company.&&
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Experience for ASIC tapout and bring up.
- Fluent English on talking, presentation and writing documents.&&
Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
Qualified candidate will perform some or all functions below:
- Participate in SOC full Chip DFT feature and architecture definition
- Responsible for DFT specification generation and review
- Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
- Perform verification on all DFT structures
- Generate DFT related timing constraints and work with PD team for timing closure
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE
- Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
-& &BS in EE & CS.&&MS preferred.
-& &MS +6 years, BS +8 years related experience
-& &Hands on working experience on ASIC DFT design and verification
-& &Familiar with entire ASIC design flow
-& &Experience with micro processor design a big plus
-& &Should have strong problem solving skills
-& &Good English hearing, speaking, reading and writing capabilities
-& &Good communication skills
Linux Graphics 2d driver
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Design, code, optimize and maintain AMD Linux graphics display driver
- AMD new graphics ASIC bring up under Linux
PREFERRED EXPERIENCE:
- Mater degree or above in C.S. or E.E.
- Good knowledge of C/C++ programming
- Good knowledge of Linux kernel programming
- Good knowledge of graphics is a plus
- Good written and verbal communication skills
- 3+ years experience in C/C++ programming
- 3+ years experience in Linux kernel development and debugging
- 3+ years experience in Linux device driver development and debugging
- Experience in graphics driver development is a plus
- Experience in XServer/X.Org development is a plus
- Fluent English language communication skills (including verbal/writing/reading), and CET-6 pass is a minimum
MTS ASIC CAD Engineer
- Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
- Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products
- Technical support and programming
- Interface with EDA venders on technology
Requirements:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
- Good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow
- Experience in ASIC design (digital design, Front-end and/or Back-end)
- Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route, signal integrity analysis, CTS design, design rule and connectivity verification, DFT ) and usage of related EDA tools
- Good written and spoken English
- Good communication skills and be able to work both independently and in a team
Highlight:
The key requirement is experience with UPF :
- UPF2.0 preferred but UPF1.0 is acceptable
- DC-T power aware synthesis
- MVRC checking on RTL used for synthesis and especially on netlist after&&synthesis
- Formality C both power aware with UPF and non-power aware
Hands on DFT implementation experience:
- DFT scan implementation using Mentor Testkompress (short term need) or Synopsys DFTMAx (long tern need)
- Understanding of scan compression logic generation and stitching of this logic into the design
- Understanding of Isolation wrappers for scan
Physical synthesis is nice to have:
- Physical synthesis C debugging synthesis with a floorplan, correlation of synthesis to physical layout (ICC placement)
MTS for ASIC Design Verification Engineer - GateSim
Description of job and responsibility:
- Understand the architecture of the chip and functional block being designed
- Build testbench and testcase for power-aware simulation
- Debug function/performance bugs of graphics chips
- Develop tools or monitors to improve verification
Requirement and Preferred Experience:
- Background in Electrical Engineering(EE) or Computer Science(CS) field
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with ASIC design or verification
- Understand low power design flow is a plus
- Experience on verilog HDL coding and debugging
- Experience on C/C++ programming and debugging(plus)
- Familiar with script(perl, tcl) program and makefile(plus)
- Familiar with SystemVerilog or SystemC (plus)
- Good written and fluent oral English
- Good communication skill and teamwork spirit
MTS GPU Firmware Development Engineer
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- A minimum of 6+ years experience on driver or embedded SW development and closely interact with HW designers (8+ years as a bachelor, 6+ years as a master)
- Hands on firmware or hardware driver development experience in an ASIC company is preferred
- Strong mix of large-scale software development ability and hardware understanding
- Proficient in C/C++ programming
- Familiar with Linux
- Hands-on experience with any one of display interface, PCI-E, and GDDR memories is preferred.
- Hands-on experience with 3D graphics is highly desired
- Strong experience with board bring up is essential
- Strong debugging and testing skills
- Strong communication skills
MTS PCB Layout Engineer
KEY RESPONSIBILITIES
- Work and communicate with layout teams in NA, architecture and execute AMD Client motherboards, graphics cards and server HST PCB layout design in SRDC
- Interface with NA technical staffs on the PCB layout related technical issues sync up,&&develop and deploy latest layout rules, execute new silicon layout trial routing
- Provide technical guidance to layout engineers in the team, ensure product requirements and design rules can be observed, mentor junior team members
- Identify program risks in terms of coverage, enablement and execution
- Collect training requirements and work out training plan to grow the PCB layout skills of the team
- Forward thinker to improve development process and drive PCB new technology innovation
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- 8+ years proven hands on experience in high speed PCB layout design for x86 PC motherboard, graphics and server products
- Prior experience in complex silicon bring up board design is highly desired
- Strong signal integrity (SI) and power integrity (PI) modeling experience is highly desired
- Skillful to operate Cadence Allegro, Concept, ProE along with strong skills in designing high speed, multi layer, high density designs, Analog/RF layout and power supply layout.
- Hands on experience to create and manage PCB library
- Highly self-motivated and a self starter and have good communications skills.&&
- Good knowledge of IPC specifications, PCB manufacturing and assembly process
- Excellent communication skills
Open GL MTS
DESCRIPTION OF DUTIES
- Implement OpenGL new features for new generation Graphic chips.
- Improve OpenGL benchmark performance.
- Work with key customers and vendors for implementation and issue solving.
- Interact with the Graphics Community .
Develop internal tools to improve development efficiency.
PREFERRED EXPERIENCE:
- Solid knowledge in C/C++ programming language, at least 5 years plus C/C++ language experience.
- Solid knowledge in Computer Graphics.
- Strong knowledge in Linux kernal, 1 year plus Linux development experience
- Strong knowledge in software development life cycle.
- Strong knowledge in debug tools usage.
- High quality team player as good team working spirits and easy going with team members.
- Prefer MS or higher education in CS or EE or Mathematic.
PD Program Manager
Job Description: The individual who fills this role will be responsible for driving programs from inception to full deployment. This individual will align all aspects of engineering and operation execution to meet business goals. This individual will interact with AMD executives and senior management team, 3rd-party partners, and possibly customers. This individual will be responsible for the management of program execution and its day-to-day activities centered around GPU development. This individual will work with engineering management to drive execution excellence, including key metrics like Time-to-Market, Time-to-Yield, and Silicon Quality Indicators. This individual will work collaboratively with the AMD Program Management community on infrastructure development and continuous process improvement. Work is strategic and tactical in nature with execution excellence being a key priority. Communication is a critical part of this role which includes interpreting/understanding business directions, explaining tactical details, and recommending solutions regarding complex program situations. Travel is expected for this role.
Job Requirements:
- Experience in managing complex, interrelated projects, programs, and functions to aggressive deadlines.
- Experience in ASIC development, including physical design.
- Experience in co-work with Physical Design manager for human resource plan according to global project schedule
- Experience in implement IT solution such as network, local disk, video conference, project share point maintenance.
- Experience in project schedule follow up and post project physical design review.
- Five years minimum related experience with two years (plus) management experience.
- BS in EE (or equivalent). Masters in EE or Engineering/Operations Management (or equivalent) preferred.
The ideal candidate will have experience with programs that can change quickly and may be speculative in nature. Candidate should be results driven, disciplined, and analytical. Candidate must exhibit very good problem solving skills, interpersonal skills, communications skills, and teamwork spirit.
SMTS - Elec. Analysis & Design(EAD)
JOB DESCRIPTION
Processor silicon interface functional and electrical validation engineer.&&In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management.
SKILLS REQUIRED
- BS-EE / BS-CE / Masters plus at least 5-8 years directly related experience. An advanced degree will be considered a plus.
- Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. Platform level electrical characterization experience with processor I/O interfaces is considered a plus.&&
- Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces
- Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications.
- Experience in software development including using languages such as Perl & Ruby to be used in silicon validation test plan development & execution
- Requires good written and oral communication skills.&&Demonstrate the ability to communicate with a variety of engineering disciplines and management.
SMTS - Graphics Board Design Engineer
KEY RESPONSIBILITIES
- Architecture the board design with best in class AMD GPU silicon, define the board design methodologies, design rules, technology roadmap
- Participate in silicon,&&board and system bring up
- Represent the team to participate in technical forum and the technical discussion on the design rules, technologies and industry specification (bus, memory, video interface, power etc)
- Understand marketing needs to ensure 'time to market' and quality and cost are balanced, maintain the technology advance and improve product competence&&
- Driving continuous improvement into existing board design and test methodologies
- Mentor junior design engineers
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English is required C verbal and written
EXPERIENCE AND SKILLS
- Bachelor or a Master of Science degree in Electrical Engineering, Computer Engineering or Computer Science
- A minimum of 10+ year hands on experience on graphics or CPU large scale silicon and board design
- Solid analog/digital mixed signal experience with silicon debug and lab tools
- Strong mix of high speed board design experience and software understanding
- Strong experience with silicon and board bring up is essential
- Strong debugging and testing skills
- PC system architecture knowledge
- Strong organization and planning skills
- Excellent communication skills
Sr&&Memory Tuning Engineer
KEY RESPONSIBILITIES
- Work with Manager, MTAG to support the qualification of memories on AMD graphics products.
- Develop and perform BIOS tuning and verify memory interface to test memories on various AMD boards.
- Qualify alternate memory sources for AMD OEM, ODM and AIB customers.
- Troubleshoot and provide solutions and perform FAs for problems related to functionality of memories on AMD boards.
- Perform Signal Integrity measurements as requested by OEM/ODM customers.
- Develop and improve memory test methodologies and procedures as the new memory technologies emerge.
- Assist in joint qualifications with memory suppliers for new die memories or new devices from new suppliers.
- Assist Field Application Engineers to support AMD customers in BIOS tuning and other memory related issues.
- Generate memory qualification reports and maintain memory AVLs.
REQUIREMENTS
- B.Sc. or M.Sc. In EE or CS or equivalent is required
- Good English required C verbal and written
- Mandarin
EXPERIENCE AND SKILLS
- At least 6+ years experience in electronic hardware development or test environment (6+ years as a bachelor, 4+ years as a master)
- Understand high-speed mix-signal multi-layer PCB design techniques
- Experience with DRAM memories and knowledge of different memory technologies is an asset.&&
- Skilful to operate high bandwidth oscilloscope for high speed signal measuring and analyzing
- Good communication skills and tact in order to set up liaison with customers and memory vendors and internal AMD departments.
- Knowledge of PC, CPU and graphics architectures
- Proven ability to effectively handle fast-pace projects
- Must be a self-motivated contributor and a strong team player
- Effective communication skills (both written and spoken) in English and Mandarin
Sr BIOS Design Engineer
PREFERRED EXPERIENCE:
- Bachelor degree or above in EE, CS, CE, with 5+ experience related to BIOS, firmware, or system software development.
- Strong Knowledge on ACPI, USB, PCIE, SATA and other PC industry standard
- Good at X86 assembly and C language
- Master at least one BIOS code base (Award, AMI, Insyde or Phoenix BIOS).
- Strong communication skills with both internal teams and customers
- UEFI experience is a big plus
Key responsibilities
- Design, develop, and debug BIOS (System Software) or UEFI Firmware for internal/external systems and platforms that use AMD CPU, AMD chipset, and 3rd party chipset.
- Be involved in day-to-day BIOS development work using PC assembly and C will need to interact with internal organizations, BIOS vendors, and customers.
- Comfortable working with PC hardware, platform, and
and the candidate must have strong system debugging skills. The following are typical tasks that the engineer will be responsible for:
- Design BIOS features required by AMD CPU
- Develop BIOS features for the new platforms designed in * Sustain existing BIOS; * Debug BIOS and s
- Assist CPU validation, platform validation, and debug engineers to develop/debug syste
- Provide consultation to internal and external customers regarding AMD features and programming requirements.
Sr. & MTS for System board deisgn
- Participates in discussions with Customers, Field Applications, Sales and Marketing to determine what hardware products are necessary to support and complement new silicon products.
- Develops and reviews comprehensive specifications for board-level and system-level products, based on a clear understanding of the function to be demonstrated across design, testing, and use of the product
- Designs board level products to meet the requirements of the project to agreed schedule, quality and cost requirements across the whole development lifecycle. Support outside manufacture venders.
- Focus on the electronic circuit design, test and debugging for the microprocessor based products such as PC desktop, mobile and server system.
- Responsible for board/system level development including schematics design, components selection, system bring-up, tuning, and functional validation and debugging.
- Develops FPGA firmware to support new board-level designs.
- Feedback and refine design rules with simulation and silicon design teams
- Negotiate solid solutions to technical issues and design challenges
- Ensure all processes are met in development
- Provides guidance for less experienced engineers
- Writes and reviews detailed technical documentation.
- Provides design assistance to Customers, Field Applications, and Sales.
- Supports resolution of customer problems which require system-level expertise.
PREFERRED EXPERIENCE:
- 5 + years experience in PC desktop, mobile or server system development or sustaining.
- Strong hardware design skills as measured by successful delivery of digital designs.
- Knowledge of design flow, product development processes, reliability verification, validation and compatibility testing.
- Experience in Microprocessor based motherboard designs in the PC Desktop, Mobile and Server markets.
- Familiar with PC, mobile or server architecture.
- Familiar with CAD Tools, including but not limited to OrCAD, Allegro, and Concept HDL.
- Familiar with Verilog, FPGA program and debug.
- Proficient with the Windows Operating System.
- Basic understanding of UNIX/Linux, software languages, and HDL sufficient to help debug system problems
- Bachelor or above degree in an Engineering or Science area.
- Ability to clearly communicate technical ideas across disciplines.
- Proficient English and Mandarin (listening, writing and speaking).
- Strong passion for achievement and career development.
- Self-motivated and able to work independently and effectively to meet time requirements.
Sr. ASIC Design Verification Engineer for Graphics Hardware
Job description:
- Understand the architecture of the chip and functional block being designed
- Build C/C++ model for simulation
- Build test bench and monitors for DUT
- Compose test plan and validation vectors to ensure functional completeness
- Debug function/performance bugs of graphics chips
Preferred Experience:
- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Should have excellent communication skills (both written and oral)
- Strong problem solving skills
Sr. SysTest Validation Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- To verify and validate hardware products designed and developed in house at AMD(ATI) using the standard qualification process developed within the hardware qualification group and participates in creating/improving all phases of test procedures and methodologies.
- Analyze the failures found in testing and support the internal design team to find the root
- Assist validation team in improving the validation methods and procedures.
- Executing and/or automating the tests including some signal integrity analysis.
- Communicate with various internal departments to resole anomalies
- Participate in issuing internal/external releasable test reports.
PREFERRED EXPERIENCE:
- Bachelor degree of electrical engineering/computer science/
- Good written and oral communication skills in both English and Chinese.
- Self-motivated and able to work independently and effectively to meet time requirements.
- Minimum 3-5 years of industrial experience in a hardware product testing or development environment
- Proficient in using electronic equipments such as digital oscilloscope, logic and network analyzer.
- Proficient in using all MS operating systems and the configuration/setting of PCs.
- Experienced in video/graphics product development and sustaining, system level hardware and software design
- Solid background in IC technology
- Experienced in board level design and development.
- Familiarity with Linux is an asset.
Staff Engineer of GFX Design Verification
Responsibility:
- Read and understand graphics specification for new hardware architecture.
- Work with NA team to write chip level test plan.
- Based on the test plan to write chip level tests to verify the function of graphics IP core.
- Debug the test to get expected result on C-model.
- Debug to locate issue of the fail on C-model and RTL-model, and push designer to fix.
Requirements:
- Master or above, major is CS, EE or Math.
- Strong program/debug ability on c/c++.
- 5 years or above experience on related task.
- Familiar to graphics algorithm like rendering/shader.
- Familiar to linux env/script is a big plus.
Staff IP-SOC DV Engineer
Job description:
- This candidate is responsible to lead a Design CAD team for Front-End ASIC Design and Verification.
- Understand the FE ASIC design flow, design verification flow, and integration flow.
- Consolidate the design and verification methodologies for graphics and micro-processor hardware.
- Develop infrastructure and release for variant IP/SOC teams.
- Explore the advanced design and verification methodologies for high efficient R&D.
- Also be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment.
Preferred Experience:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Scripting language experience a plus (perl, ruby, tcl, etc.)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Should have excellent communication skills (both written and oral)
- Strong problem solving skills
Staff Physical Design Engineer
- PhD with 3+ years of industrial experience or MSEE with 6+ years of industrial experience in ASIC design
- 3+ years or more years of experience in physical design of deep submicron digital ASIC chips
- Hands on experience in large scale ASIC chip physical design
- Knowledgeable in all aspects of deep submicron ASIC design flow
- Successfully gone through several complete product development cycles
- Demonstrate leadership and work well with cross-functional teams
- Good listening, writing and speaking English
- Good communication skills, strong interpersonal skills and the flexibility
- Dedicated, hard working and good team player
- Familiar with Back-End (physical design) EDA tools
- Familiar with Front-End EDA tools is a plus
- Familiar with Unix/Linux environment and good at scripts
Staff System Design Verfication Engineer
- Have passion to learn new technology.
- strong skills in c++, systemc or verilog
- initiative, aggressive, and responsible
- Good at solving problem
-&&Good communication (both in Chinese and English) and team-work skills
- Good at self-learning
- Deep understanding about the verification methodology is an option
- Good understanding about memory virtualization or PCIE is an option
UID854902&帖子4&精华0&积分0&资产0 信元&发贴收入1555 信元&推广收入0 信元&附件收入0 信元&下载支出6663 信元&阅读权限10&在线时间53 小时&注册时间&最后登录&
AMD好公司啊，看起来挺不错的，支持一下...
UID466150&帖子1081&精华0&积分18001&资产18001 信元&发贴收入5595 信元&推广收入0 信元&附件收入0 信元&下载支出17645 信元&阅读权限70&在线时间882 小时&注册时间&最后登录&
说明流动性很强啊
UID854902&帖子4&精华0&积分0&资产0 信元&发贴收入1555 信元&推广收入0 信元&附件收入0 信元&下载支出6663 信元&阅读权限10&在线时间53 小时&注册时间&最后登录&
楼主，发简历到你邮箱了，谢谢
UID7789&帖子326&精华0&积分6015&资产6015 信元&发贴收入1990 信元&推广收入0 信元&附件收入936 信元&下载支出9648 信元&阅读权限50&在线时间1213 小时&注册时间&最后登录&
把简历给你，你转给了HR，就意味着什么了？
UID466150&帖子1081&精华0&积分18001&资产18001 信元&发贴收入5595 信元&推广收入0 信元&附件收入0 信元&下载支出17645 信元&阅读权限70&在线时间882 小时&注册时间&最后登录&
都是来赚推荐费的，据说有人能赚到上W
UID855418&帖子5&精华0&积分13&资产13 信元&发贴收入25 信元&推广收入0 信元&附件收入0 信元&下载支出3315 信元&阅读权限10&在线时间33 小时&注册时间&最后登录&
把简历给你，你转给了HR，就意味着什么了？
TomPaul 发表于
& & 内部推荐，意味着如果不是太差，就可以不用笔试，直接进入面试了
UID855293&帖子69&精华0&积分80&资产80 信元&发贴收入360 信元&推广收入0 信元&附件收入0 信元&下载支出3037 信元&阅读权限10&在线时间19 小时&注册时间&最后登录&
已经发简历给你了，谢谢
UID855942&帖子18&精华0&积分80&资产80 信元&发贴收入90 信元&推广收入0 信元&附件收入0 信元&下载支出2284 信元&阅读权限10&在线时间9 小时&注册时间&最后登录&
友情支持一下.......
UID846338&帖子73&精华0&积分13&资产13 信元&发贴收入390 信元&推广收入0 信元&附件收入0 信元&下载支出502 信元&阅读权限10&在线时间11 小时&注册时间&最后登录&
Read!!!!!!!!!!!!!!!!!!
[通过 QQ、MSN 分享给朋友]