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由上而下层层剖析：细说pci express 1.1新版精髓
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维普资讯 http://www.cqvip.com
TE H O OGY
Et~~T层层剖析
mi~PCIExpress 111新版精髓
资深电子技术专栏作家暨知识日文与信息日文研究者
目前市面上可以见到许多PCIExpress产品，从芯片组主板到接 口卡不一而足。但插拔大会 (Plugfest)
的举办，以及市面上的英文原版参考书，都是以2003年4月的1．0a版为参考基准，2005年3月推出
的1．1版本究竟作了哪些更动、增加了什么新功能、会不会冲击到原来的设计 ，成为业界人士关注的
Interrupt)机制，还增加 了MSI—x
对 RootComplex器件的定义
中断方式 (MSI—xcapability)。
做 了功能性追 加 ，允许器件 中 内
站在 传 输协 议面 向的观点来 看 ，
MSI中断机制在PCI2．3的规
建端点装置 (Endpoint)及一个事
它 的复杂 度 也相 当高 。虽然 在
格中就有很清楚的记载，基本上 ，
件收集器 (EventCollector)的区
Devcon一2005开 发者会议上提 出了
它是一种存储 器写入 (Memory
块。集成端点 的含意就是从 此之
1．1版主要 更新 内容的简报 图片和
Write)的数据 交易。而 MSI—x其
后 ，RootComplex器件也 可视为端
文件 ，但 真的不是很容易了解 。为
实就是MSI机制的加强版 ，在PCI
点装置 ，其 中的事件收集器 可 以
了使读者 有更系统化 的感受而不
规格 3．0版 中有所描述 。
用来终结 内部端点所产生 的PME
觉得厌烦 ，下面将从 上而下来谈
PCIExpress中所规范的开关元
消 息 或 错 误 ?肖息 (E rrOr
论主要的更动之处 。
器件是不能将封包作分割的，而 1．1
Messages)。
版新规格中，允许对等式 (Peer-to-
这样一 来，PCIExpress连接
从系统架构观察
peer)数据 交易连接的根联合体
型态就 可能存 在三 种端 点装置 ：
在 中断处理方面 ，除了保 留
(RootComplex)器件切割封包成较
沿 用 旧 PCI规 范 的 “LegacY
endpoints”
原有 的MSI(MessageSignaled
小的格式，满足不同总线区段需求。
、 使用 PCIe新机能的
一 图2EventCollector及端点装■集成
(IntegratedEndpoint)的追加
维普资讯 http://www.cqvip.com
“NativePCIExpressEndpoint”及
从封包为本的数据交易观察
个 Dw 的字 节 使 能 (BYte
内建集成端点 的 “RootComplex”
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PCI Express Base Specification：（PCI Express基础规范）.pdf 704页
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PCI Express Base Specification：（PCI Express基础规范）
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PCI Express(R)
Base Specification
Revision 2.1
March 4, 2009
Revision History
Initial release.
07/22/2002
Incorporated Errata C1-C66 and E1-E4.17.
04/15/2003
Incorporated approved Errata and ECNs.
03/28/2005
Added 5.0 GT/s data rate and incorporated approved Errata and ECNs.
12/20/2006
Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
03/04/2009
(February 27, 2009), and added the following ECNs:
Internal Error Reporting ECN (April 24, 2008)
Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
Atomic Operations ECN (January 15, 2008, approved by PWG April 17,
Resizable BAR Capability ECN (January 22, 2008, updated and
approved by PWG April 24, 2008)
Dynamic Power Allocation ECN (May 24, 2008)
ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
Latency Tolerance Reporting ECN (22 January 2008, updated 14
August 2008)
Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last
updated June 4, 2007)
Extended Tag Enable Default ECN (September 5, 2008)
TLP Processing Hints E
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pcie 2.0 总线规范
PCI Express? Base Specification Revision 2.0December 20, 20062Revision Revision History DATE 1.0 Initial release. 07/22/02 1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/03 1.1 Incorporated approved Errata and ECNs. 03/28/05 2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/06PCI-SIG? disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail:
Phone: 503-619-0569 Fax: 503-644-6708 Technical Support
DISCLAIMER This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright ?
PCI-SIGPCI EXPRESS BASE SPECIFICATION, REV. 2.0 3ContentsOBJECTIVE OF THE SPECIFICATION.................................................................................... 21 DOCUMENT ORGANIZATION ................................................................................................ 21 DOCUMENTATION CONVENTIONS...................................................................................... 22 TERMS AND ACRONYMS........................................................................................................ 23 REFERENCE DOCUMENTS...................................................................................................... 29 1. INTRODUCTION ........................................................................................................... ..... 31 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 31 1.2. PCI EXPRESS LINK......................................................................................................... 33 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 35 1.3.1. Root Complex........................................................................................................ 35 1.3.2. Endpoints .............................................................................................................. 36 1.3.3. Switch.................................................................................................................... 39 1.3.4. Root Complex Event Collector.............................................................................. 40 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 40 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 40 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 41 1.5.1. Transaction Layer.................................................................................................42 1.5.2. Data Link Layer .................................................................................................... 42 1.5.3. Physical Layer ...................................................................................................... 43 1.5.4. Layer Functions and Services............................................................................... 43 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 47 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 47 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 48 2.1.2. Packet Format Overview ...................................................................................... 50 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 51 2.2.1. Common Packet Header Fields ............................................................................ 51 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 54 2.2.3. TLP Digest Rules .................................................................................................. 56 2.2.4. Routing and Addressing Rules .............................................................................. 56 2.2.5. First/Last DW Byte Enables Rules........................................................................ 59 2.2.6. Transaction Descriptor......................................................................................... 61 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 66 2.2.8. Message Request Rules......................................................................................... 69 2.2.9. Completion Rules.................................................................................................. 80 2.3. HANDLING OF RECEIVED TLPS...................................................................................... 82 2.3.1. Request Handling Rules........................................................................................ 85PCI EXPRESS BASE SPECIFICATION, REV. 2.0 42.3.2. Completion Handling Rules.................................................................................. 98 2.4. TRANSACTIONORDERING............................................................................................ 100 2.4.1. Transaction Ordering Rules ............................................................................... 100 2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 104 2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 105 2.5. VIRTUAL CHANNEL (VC)MECHANISM........................................................................ 105 2.5.1. Virtual Channel Identification (VC ID) .............................................................. 108 2.5.2. TC to VC Mapping.............................................................................................. 109 2.5.3. VC and TC Rules................................................................................................. 110 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 111 2.6.1. Flow Control Rules............................................................................................. 112 2.7. DATA INTEGRITY ......................................................................................................... 122 2.7.1. ECRC Rules ........................................................................................................ 123 2.7.2. Error Forwarding ............................................................................................... 127 2.8. COMPLETION TIMEOUT MECHANISM........................................................................... 129 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 130 2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 130 2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 131 3. DATA LINK LAYER SPECIFICATION.......................................................................... 133 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 133 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 135 3.2.1. Data Link Control and Management State Machine Rules ................................ 136 3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 138 3.3.1. Flow Control Initialization State Machine Rules ...............................................138 3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 142 3.4.1. Data Link Layer Packet Rules ............................................................................ 142 3.5. DATA INTEGRITY ......................................................................................................... 147 3.5.1. Introduction......................................................................................................... 147 3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 147 3.5.3. LCRC and Sequence Number (TLP Receiver) .................................................... 159 4. PHYSICAL LAYER SPECIFICATION............................................................................ 167 4.1. INTRODUCTION ............................................................................................................ 167 4.2. LOGICAL SUB-BLOCK................................................................................................... 167 4.2.1. Symbol Encoding ................................................................................................ 168 4.2.2. Framing and Application of Symbols to Lanes................................................... 171 4.2.3. Data Scrambling ................................................................................................. 174 4.2.4. Link Initialization and Training.......................................................................... 176 4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 188 4.2.6. Link Training and Status State Rules.................................................................. 192 4.2.7. Clock Tolerance Compensation.......................................................................... 237 4.2.8. Compliance Pattern ............................................................................................ 239 4.2.9. Modified Compliance Pattern............................................................................. 240 4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 241 4.3.1. Maintaining Backwards Compatibility ............................................................... 241 4.3.2. Jitter Budgeting and Measurement..................................................................... 243PCI EXPRESS BASE SPECIFICATION, REV. 2.0 54.3.3. Transmitter Specification.................................................................................... 244 4.3.4. Receiver Specification......................................................................................... 259 4.3.5. Transmitter and Receiver DC Specifications...................................................... 273 4.3.6. Channel Specifications........................................................................................ 278 4.3.7. Reference Clock Specifications........................................................................... 285 5. POWER MANAGEMENT................................................................................................. 293 5.1. OVERVIEW ................................................................................................................... 293 5.1.1. Statement of Requirements.................................................................................. 294 5.2. LINK STATE POWER MANAGEMENT............................................................................. 294 5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 299 5.3.1. Device Power Management States (D-States) of a Function.............................. 299 5.3.2. PM Software Control of the Link Power Management State.............................. 303 5.3.3. Power Management Event Mechanisms ............................................................. 308 5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 315 5.4.1. Active State Power Management (ASPM) .......................................................... 315 5.5. AUXILIARY POWER SUPPORT....................................................................................... 331 5.5.1. Auxiliary Power Enabling................................................................................... 331 5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 332 6. SYSTEM ARCHITECTURE ............................................................................................. 335 6.1. INTERRUPT AND PME SUPPORT ................................................................................... 335 6.1.1. Rationale for PCI Express Interrupt Model........................................................335 6.1.2. PCI Compatible INTx Emulation........................................................................ 336 6.1.3. INTx Emulation Software Model ........................................................................ 336 6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 336 6.1.5. PME Support....................................................................................................... 338 6.1.6. Native PME Software Model .............................................................................. 338 6.1.7. Legacy PME Software Model ............................................................................. 339 6.1.8. Operating System Power Management Notification........................................... 339 6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 339 6.2. ERROR SIGNALING AND LOGGING................................................................................ 340 6.2.1. Scope................................................................................................................... 340 6.2.2. Error Classification ............................................................................................ 340 6.2.3. Error Signaling ................................................................................................... 342 6.2.4. Error Logging ..................................................................................................... 349 6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 352 6.2.6. Error Message Controls ..................................................................................... 354 6.2.7. Error Listing and Rules ...................................................................................... 355 6.2.8. Virtual PCI Bridge Error Handling.................................................................... 359 6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 360 6.3.1. Introduction and Scope ....................................................................................... 360 6.3.2. TC/VC Mapping and Example Usage................................................................. 361 6.3.3. VC Arbitration .................................................................................................... 363 6.3.4. Isochronous Support ...........................................................................................371 6.4. DEVICE SYNCHRONIZATION......................................................................................... 374 6.5. LOCKED TRANSACTIONS.............................................................................................. 375PCI EXPRESS BASE SPECIFICATION, REV. 2.0 66.5.1. Introduction......................................................................................................... 375 6.5.2. Initiation and Propagation of Locked Transactions - Rules............................... 376 6.5.3. Switches and Lock - Rules................................................................................... 377 6.5.4. PCI Express/PCI Bridges and Lock - Rules ....................................................... 377 6.5.5. Root Complex and Lock - Rules.......................................................................... 378 6.5.6. Legacy Endpoints................................................................................................ 378 6.5.7. PCI Express Endpoints ....................................................................................... 378 6.6. PCI EXPRESS RESET RULES....................................................................................... 378 6.6.1. Conventional Reset ............................................................................................. 378 6.6.2. Function-Level Reset (FLR)................................................................................ 381 6.7. PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 384 6.7.1. Elements of Hot-Plug.......................................................................................... 385 6.7.2. Registers Grouped by Hot-Plug Element Association........................................ 391 6.7.3. PCI Express Hot-Plug Events............................................................................. 393 6.7.4. Firmware Support for Hot-Plug ......................................................................... 396 6.8. POWER BUDGETING CAPABILITY ................................................................................. 396 6.8.1. System Power Budgeting Process Recommendations......................................... 397 6.9. SLOT POWER LIMIT CONTROL ..................................................................................... 397 6.10. ROOT COMPLEX TOPOLOGY DISCOVERY.................................................................400 6.11. LINK SPEED MANAGEMENT ..................................................................................... 402 6.12. ACCESS CONTROL SERVICES (ACS) ........................................................................ 403 6.12.1. ACS Component Capability Requirements ......................................................... 404 6.12.2. Interoperability ................................................................................................... 408 6.12.3. ACS Peer-to-Peer Control Interactions.............................................................. 408 6.12.4. ACS Violation Error Handling ........................................................................... 409 6.12.5. ACS Redirection Impacts on Ordering Rules ..................................................... 410 7. SOFTWARE INITIALIZATION AND CONFIGURATION............................................ 413 7.1. CONFIGURATION TOPOLOGY........................................................................................ 413 7.2. PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 414 7.2.1. PCI 3.0 Compatible Configuration Mechanism ................................................. 415 7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM).................. 416 7.2.3. Root Complex Register Block ............................................................................. 420 7.3. CONFIGURATION TRANSACTION RULES....................................................................... 421 7.3.1. Device Number.................................................................................................... 421 7.3.2. Configuration Transaction Addressing............................................................... 422 7.3.3. Configuration Request Routing Rules................................................................. 422 7.3.4. PCI Special Cycles.............................................................................................. 423 7.4. CONFIGURATION REGISTER TYPES .............................................................................. 424 7.5. PCI-COMPATIBLE CONFIGURATION REGISTERS........................................................... 425 7.5.1. Type 0/1 Common Configuration Space............................................................. 426 7.5.2. Type 0 Configuration Space Header...................................................................432 7.5.3. Type 1 Configuration Space Header................................................................... 434 7.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE.................................................. 438 7.7. MSI AND MSI-X CAPABILITY STRUCTURES ................................................................ 439 7.8. PCI EXPRESS CAPABILITY STRUCTURE........................................................................ 440 7.8.1. PCI Express Capability List Register (Offset 00h) ............................................. 441PCI EXPRESS BASE SPECIFICATION, REV. 2.0 77.8.2. PCI Express Capabilities Register (Offset 02h) ................................................. 442 7.8.3. Device Capabilities Register (Offset 04h) .......................................................... 444 7.8.4. Device Control Register (Offset 08h) ................................................................. 449 7.8.5. Device Status Register (Offset 0Ah).................................................................... 455 7.8.6. Link Capabilities Register (Offset 0Ch).............................................................. 458 7.8.7. Link Control Register (Offset 10h) ..................................................................... 462 7.8.8. Link Status Register (Offset 12h) ........................................................................ 469 7.8.9. Slot Capabilities Register (Offset 14h) ............................................................... 472 7.8.10. Slot Control Register (Offset 18h) ...................................................................... 474 7.8.11. Slot Status Register (Offset 1Ah)......................................................................... 478 7.8.12. Root Control Register (Offset 1Ch) .................................................................... 480 7.8.13. Root Capabilities Register (Offset 1Eh) ............................................................. 482 7.8.14. Root Status Register (Offset 20h)........................................................................ 482 7.8.15. Device Capabilities 2 Register (Offset 24h) ....................................................... 483 7.8.16. Device Control 2 Register (Offset 28h) .............................................................. 485 7.8.17. Device Status 2 Register (Offset 2Ah).................................................................487 7.8.18. Link Capabilities 2 Register (Offset 2Ch)........................................................... 487 7.8.19. Link Control 2 Register (Offset 30h) .................................................................. 487 7.8.20. Link Status 2 Register (Offset 32h) ..................................................................... 492 7.8.21. Slot Capabilities 2 Register (Offset 34h) ............................................................ 492 7.8.22. Slot Control 2 Register (Offset 38h) ................................................................... 492 7.8.23. Slot Status 2 Register (Offset 3Ah)...................................................................... 492 7.9. PCI EXPRESS EXTENDED CAPABILITIES....................................................................... 493 7.9.1. Extended Capabilities in Configuration Space................................................... 493 7.9.2. Extended Capabilities in the Root Complex Register Block............................... 493 7.9.3. PCI Express Enhanced Capability Header......................................................... 494 7.10. ADVANCED ERROR REPORTING CAPABILITY ........................................................... 495 7.10.1. Advanced Error Reporting Enhanced Capability Header (Offset 00h).............. 496 7.10.2. Uncorrectable Error Status Register (Offset 04h).............................................. 497 7.10.3. Uncorrectable Error Mask Register (Offset 08h)............................................... 498 7.10.4. Uncorrectable Error Severity Register (Offset 0Ch).......................................... 499 7.10.5. Correctable Error Status Register (Offset 10h).................................................. 501 7.10.6. Correctable Error Mask Register (Offset 14h)................................................... 502 7.10.7. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 503 7.10.8. Header Log Register (Offset 1Ch) ...................................................................... 504 7.10.9. Root Error Command Register (Offset 2Ch) ...................................................... 505 7.10.10. Root Error Status Register (Offset 30h).......................................................... 506 7.10.11. Error Source Identification Register (Offset 34h) ..........................................509 7.11. VIRTUAL CHANNEL CAPABILITY ............................................................................. 510 7.11.1. Virtual Channel Enhanced Capability Header................................................... 512 7.11.2. Port VC Capability Register 1 ............................................................................ 513 7.11.3. Port VC Capability Register 2 ............................................................................ 514 7.11.4. Port VC Control Register.................................................................................... 515 7.11.5. Port VC Status Register ...................................................................................... 516 7.11.6. VC Resource Capability Register ....................................................................... 517 7.11.7. VC Resource Control Register............................................................................ 519PCI EXPRESS BASE SPECIFICATION, REV. 2.0 87.11.8. VC Resource Status Register .............................................................................. 521 7.11.9. VC Arbitration Table .......................................................................................... 522 7.11.10. Port Arbitration Table .................................................................................... 523 7.12. DEVICE SERIAL NUMBER CAPABILITY..................................................................... 525 7.12.1. Device Serial Number Enhanced Capability Header (Offset 00h)..................... 526 7.12.2. Serial Number Register (Offset 04h)................................................................... 527 7.13. PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ............................ 527 7.13.1. Root Complex Link Declaration Enhanced Capability Header ......................... 529 7.13.2. Element Self Description..................................................................................... 530 7.13.3. Link Entries......................................................................................................... 531 7.14. PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY................... 535 7.14.1. Root Complex Internal Link Control Enhanced Capability Header .................. 535 7.14.2. Root Complex Link Capabilities Register...........................................................536 7.14.3. Root Complex Link Control Register.................................................................. 538 7.14.4. Root Complex Link Status Register..................................................................... 540 7.15. POWER BUDGETING CAPABILITY............................................................................. 541 7.15.1. Power Budgeting Enhanced Capability Header (Offset 00h)............................. 541 7.15.2. Data Select Register (Offset 04h) ....................................................................... 542 7.15.3. Data Register (Offset 08h).................................................................................. 542 7.15.4. Power Budget Capability Register (Offset 0Ch)................................................. 545 7.16. ACS EXTENDED CAPABILITY .................................................................................. 545 7.16.1. ACS Extended Capability Header (Offset 00h) .................................................. 546 7.16.2. ACS Capability Register (Offset 04h) ................................................................. 546 7.16.3. ACS Control Register (Offset 06h) ..................................................................... 548 7.16.4. Egress Control Vector (Offset 08h) .................................................................... 549 7.17. PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY ...................................................................................................................... ....... 551 7.17.1. Root Complex Event Collector Endpoint Association Enhanced Capability Header ............................................................................................................................. 551 7.17.2. Association Bitmap for Root Complex Integrated Endpoints ............................. 552 7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY ................................................ 552 7.18.1. MFVC Enhanced Capability Header.................................................................. 553 7.18.2. Port VC Capability Register 1 ............................................................................ 554 7.18.3. Port VC Capability Register 2 ............................................................................ 556 7.18.4. Port VC Control Register.................................................................................... 557 7.18.5. Port VC Status Register ......................................................................................558 7.18.6. VC Resource Capability Register ....................................................................... 558 7.18.7. VC Resource Control Register............................................................................ 560 7.18.8. VC Resource Status Register .............................................................................. 562 7.18.9. VC Arbitration Table .......................................................................................... 563 7.18.10. Function Arbitration Table ............................................................................. 563 7.19. VENDOR-SPECIFIC CAPABILITY ............................................................................... 565 7.19.1. Vendor-Specific Enhanced Capability Header (Offset 00h)............................... 566 7.19.2. Vendor-Specific Header (Offset 04h).................................................................. 567 7.20. RCRB HEADER CAPABILITY ................................................................................... 568 7.20.1. RCRB Header Enhanced Capability Header (Offset 00h) ................................. 568PCI EXPRESS BASE SPECIFICATION, REV. 2.0 97.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)........................................... 569 7.20.3. RCRB Capabilities (Offset 08h).......................................................................... 570 7.20.4. RCRB Control (Offset 0Ch) ................................................................................ 570 A. ISOCHRONOUS APPLICATIONS................................................................................... 571 A.1. INTRODUCTION ............................................................................................................ 571 A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ........................................... 573 A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ............................. 574 A.2.2. Isochronous Payload Size ................................................................................... 575 A.2.3. Isochronous Bandwidth Allocation..................................................................... 575 A.2.4. Isochronous Transaction Latency....................................................................... 576A.2.5. An Example Illustrating Isochronous Parameters.............................................. 577 A.3. ISOCHRONOUS TRANSACTION RULES........................................................................... 578 A.4. TRANSACTION ORDERING............................................................................................ 578 A.5. ISOCHRONOUS DATA COHERENCY............................................................................... 578 A.6. FLOW CONTROL........................................................................................................... 579 A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION....................................................... 579 A.7.1. Isochronous Bandwidth of PCI Express Links.................................................... 579 A.7.2. Isochronous Bandwidth of Endpoints ................................................................. 579 A.7.3. Isochronous Bandwidth of Switches ................................................................... 579 A.7.4. Isochronous Bandwidth of Root Complex........................................................... 580 A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS..................................................... 580 A.8.1. An Endpoint as a Requester................................................................................ 580 A.8.2. An Endpoint as a Completer ............................................................................... 580 A.8.3. Switches............................................................................................................... 581 A.8.4. Root Complex...................................................................................................... 582 B. SYMBOL ENCODING...................................................................................................... 583 C. PHYSICAL LAYER APPENDIX...................................................................................... 593 C.1. DATA SCRAMBLING ..................................................................................................... 593 D. REQUEST DEPENDENCIES............................................................................................ 599 ACKNOWLEDGEMENTS............................................................................................. ........... 603PCI EXPRESS BASE SPECIFICATION, REV. 2.0 10FiguresFIGURE 1-1: PCI EXPRESS LINK.................................................................................................... 33 FIGURE 1-2: EXAMPLE TOPOLOGY................................................................................................ 35 FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 39 FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 41 FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 42 FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER.............................. 47 FIGURE 2-2: SERIAL VIEW OF A TLP............................................................................................. 50 FIGURE 2-3: GENERIC TLP FORMAT............................................................................................. 50 FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 52 FIGURE 2-5: 64-BIT ADDRESS ROUTING........................................................................................ 56 FIGURE 2-6: 32-BIT ADDRESS ROUTING........................................................................................ 57 FIGURE 2-7: ID ROUTING WITH 4DWHEADER ............................................................................ 58 FIGURE 2-8: ID ROUTING WITH 3DWHEADER ............................................................................ 59 FIGURE 2-9: LOCATION OF BYTE ENABLES IN TLP HEADER......................................................... 59 FIGURE 2-10: TRANSACTION DESCRIPTOR .................................................................................... 61 FIGURE 2-11: TRANSACTION ID.................................................................................................... 62 FIGURE 2-12: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 64 FIGURE 2-13: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY........................ 66 FIGURE 2-14: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY........................ 67 FIGURE 2-15: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS.............................................. 67 FIGURE 2-16: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 68 FIGURE 2-17: MESSAGE REQUEST HEADER .................................................................................. 69FIGURE 2-18: HEADER FOR VENDOR-DEFINED MESSAGES ........................................................... 78 FIGURE 2-19: COMPLETION HEADER FORMAT .............................................................................. 81 FIGURE 2-20: COMPLETER ID ....................................................................................................... 81 FIGURE 2-21: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................... 83 FIGURE 2-22: FLOWCHART FOR SWITCH HANDLING OF TLPS....................................................... 85 FIGURE 2-23: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ............................................. 90 FIGURE 2-24: VIRTUAL CHANNEL CONCEPT C AN ILLUSTRATION .............................................. 107 FIGURE 2-25: VIRTUAL CHANNEL CONCEPT C SWITCH INTERNALS (UPSTREAM FLOW) ............. 107 FIGURE 2-26: AN EXAMPLE OF TC/VC CONFIGURATIONS.......................................................... 110 FIGURE 2-27: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER..................... 111 FIGURE 2-28: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY PROTECTION ..................................................................................................................... ... 126 FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 133 FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE.................................. 135 FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE.................................................... 141 FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 142 FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK....................................... 144 FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 144 FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 144 FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC............................................ 144 FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 145PCI EXPRESS BASE SPECIFICATION, REV. 2.0 11FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKETFORMAT ...................................... 145 FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 146 FIGURE 3-12: TLP WITH LCRC AND SEQUENCE NUMBER APPLIED ........................................... 147 FIGURE 3-13: TLP FOLLOWING APPLICATION OF SEQUENCE NUMBER AND RESERVED BITS ..... 149 FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 151 FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART...................................................... 157 FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART.......................................................... 158 FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 162 FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER.......................................... 167 FIGURE 4-2: CHARACTER TO SYMBOL MAPPING......................................................................... 168 FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 169 FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 169 FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 172 FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 173 FIGURE 4-7: FRAMED TLP ON A X1 LINK.................................................................................... 173 FIGURE 4-8: FRAMED TLP ON A X2 LINK.................................................................................... 174 FIGURE 4-9: FRAMED TLP ON A X4 LINK.................................................................................... 174 FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL............................................................... 176 FIGURE 4-11: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 194 FIGURE 4-12: DETECT SUBSTATE MACHINE ............................................................................... 196 FIGURE 4-13: POLLING SUBSTATE MACHINE .............................................................................. 201 FIGURE 4-14: CONFIGURATION SUBSTATE MACHINE.................................................................. 214 FIGURE 4-15: RECOVERY SUBSTATEMACHINE........................................................................... 223 FIGURE 4-16: L0S SUBSTATE MACHINE ...................................................................................... 228 FIGURE 4-17: L1 SUBSTATE MACHINE........................................................................................ 230 FIGURE 4-18: L2 SUBSTATE MACHINE........................................................................................ 231 FIGURE 4-19: LOOPBACK SUBSTATE MACHINE........................................................................... 236 FIGURE 4-20: TRANSMITTER, CHANNEL, AND RECEIVER BOUNDARIES ...................................... 242 FIGURE 4-21: PLOT OF TRANSMITTER HPF FILTER FUNCTIONS.................................................. 245 FIGURE 4-22: TRANSMITTER MARGINING VOLTAGE LEVELS AND CODES .................................. 246 FIGURE 4-23: REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S TRANSMITTER..................... 250 FIGURE 4-24: ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S TRANSMITTER ................. 251 FIGURE 4-25: SINGLE-ENDED AND DIFFERENTIAL LEVELS.......................................................... 252 FIGURE 4-26: FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB DE-EMPHASIS 253 FIGURE 4-27: LOW SWING TX PARAMETERS............................................................................... 253 FIGURE 4-28: RISE AND FALL TIME DEFINITIONS ....................................................................... 254 FIGURE 4-29: MINIMUM PULSE WIDTH DEFINITION ................................................................... 254 FIGURE 4-30: FULL SWING TX PARAMETERS SHOWING DE-EMPHASIS ....................................... 255 FIGURE 4-31: MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE DIAGRAM...... 256 FIGURE 4-32: ALGORITHM TO REMOVE DE-EMPHASIS INDUCED JITTER..................................... 257 FIGURE 4-33: EXAMPLE OF DE-EMPHASIS JITTER REMOVAL....................................................... 257 FIGURE 4-34: TX PACKAGE PLUS DIE RETURN LOSS S11 ............................................................. 259 FIGURE 4-35: SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE LOAD ..... 261 FIGURE 4-36: SETUP FOR TESTING RECEIVER ............................................................................. 261 FIGURE 4-37: CALIBRATION CHANNELVALIDATION .................................................................. 264 FIGURE 4-38: CALIBRATION CHANNEL SHOWING TMIN-PULSE...................................................... 264PCI EXPRESS BASE SPECIFICATION, REV. 2.0 12FIGURE 4-39: CALIBRATION CHANNEL |S11| PLOT WITH TOLERANCE LIMITS .............................. 265 FIGURE 4-40: RECEIVER RETURN LOSS MASK FOR 5.0 GT/S ..................................................... 269 FIGURE 4-41: RECEIVER EYE MARGINS...................................................................................... 270 FIGURE 4-42: SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX SWING.................. 271 FIGURE 4-43: EXIT FROM IDLE VOLTAGE AND TIME MARGINS................................................... 272 FIGURE 4-44: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF CAPACITOR............................ 277 FIGURE 4-45: BEACON,WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF CAPACITOR........... 277 FIGURE 4-46: SIMULATION ENVIRONMENT FOR CHARACTERIZING CHANNEL............................. 280 FIGURE 4-47: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION RESULTS................... 283 FIGURE 4-48: MULTI-SEGMENT CHANNEL EXAMPLE.................................................................. 284 FIGURE 4-49: COMMON REFCLK RX ARCHITECTURE.................................................................. 286 FIGURE 4-50: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX ARCHITECTURE287 FIGURE 4-51: DATA DRIVING ARCHITECTURE ............................................................................ 289 FIGURE 4-52: REFCLK TEST SETUP ............................................................................................. 291 FIGURE 4-53: SEPARATE REFCLK ARCHITECTURE ...................................................................... 292 FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 297 FIGURE 5-2: ENTRY INTO THE L1 LINK STATE............................................................................ 304 FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT........................ 307 FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING. 310 FIGURE 5-5: A CONCEPTUAL PME CONTROL STATEMACHINE.................................................. 314 FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED)................ 324 FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 325 FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 326 FIGURE 6-1: ERROR CLASSIFICATION.......................................................................................... 341 FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING OPERATIONS ..................................................................................................................... ... 353 FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 354 FIGURE 6-4: TC FILTERING EXAMPLE......................................................................................... 362 FIGURE 6-5: TC TO VCMAPPING EXAMPLE ............................................................................... 362 FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS.................. 364 FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH................ 364 FIGURE 6-8: SWITCH ARBITRATION STRUCTURE......................................................................... 365 FIGURE 6-9: VC ID AND PRIORITY ORDER C AN EXAMPLE......................................................... 367 FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL.............................................................. 370 FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 401 FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS................................ 402 FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 414 FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 414 FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT...................................................... 415 FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER............................................................ 426 FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER................................................................ 433 FIGURE 7-6: TYPE 1 CONFIGURATION SPACEHEADER................................................................ 434 FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER..................................................... 438 FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 439 FIGURE 7-9: PCI EXPRESS CAPABILITY STRUCTURE................................................................... 441 FIGURE 7-10: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 441PCI EXPRESS BASE SPECIFICATION, REV. 2.0 13FIGURE 7-11: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 442 FIGURE 7-12: DEVICE CAPABILITIES REGISTER .......................................................................... 444 FIGURE 7-13: DEVICE CONTROL REGISTER................................................................................. 449 FIGURE 7-14: DEVICE STATUS REGISTER.................................................................................... 456 FIGURE 7-15: LINK CAPABILITIES REGISTER............................................................................... 458 FIGURE 7-16: LINK CONTROL REGISTER..................................................................................... 462 FIGURE 7-17: LINK STATUS REGISTER........................................................................................ 469 FIGURE 7-18: SLOT CAPABILITIES REGISTER .............................................................................. 472 FIGURE 7-19: SLOT CONTROL REGISTER..................................................................................... 474 FIGURE 7-20: SLOT STATUS REGISTER ....................................................................................... 478 FIGURE 7-21: ROOT CONTROL REGISTER.................................................................................... 480 FIGURE 7-22: ROOT CAPABILITIES REGISTER.............................................................................. 482 FIGURE 7-23: ROOT STATUS REGISTER....................................................................................... 482 FIGURE 7-24: DEVICE CAPABILITIES 2 REGISTER........................................................................ 483 FIGURE 7-25: DEVICE CONTROL 2 REGISTER .............................................................................. 485 FIGURE 7-26: LINK CONTROL 2 REGISTER .................................................................................. 487 FIGURE 7-27: LINK STATUS 2REGISTER ..................................................................................... 492 FIGURE 7-28: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT.................................. 493 FIGURE 7-29: PCI EXPRESS ENHANCED CAPABILITY HEADER.................................................... 494 FIGURE 7-30: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE .......................................................................................................................................... ... 495 FIGURE 7-31: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER ....................... 496 FIGURE 7-32: UNCORRECTABLE ERROR STATUS REGISTER ........................................................ 497 FIGURE 7-33: UNCORRECTABLE ERROR MASK REGISTER........................................................... 498 FIGURE 7-34: UNCORRECTABLE ERROR SEVERITY REGISTER..................................................... 499 FIGURE 7-35: CORRECTABLE ERROR STATUS REGISTER............................................................. 501 FIGURE 7-36: CORRECTABLE ERROR MASK REGISTER ............................................................... 502 FIGURE 7-37: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 503 FIGURE 7-38: HEADER LOG REGISTER ........................................................................................ 504 FIGURE 7-39: ROOT ERROR COMMAND REGISTER ...................................................................... 505 FIGURE 7-40: ROOT ERROR STATUS REGISTER ........................................................................... 507 FIGURE 7-41: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 509 FIGURE 7-42: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 511 FIGURE 7-43: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER.......................................... 512 FIGURE 7-44: PORT VC CAPABILITY REGISTER 1 ....................................................................... 513 FIGURE 7-45: PORT VC CAPABILITY REGISTER 2 ....................................................................... 514 FIGURE 7-46: PORT VC CONTROL REGISTER .............................................................................. 515 FIGURE 7-47: PORT VC STATUS REGISTER ................................................................................. 516 FIGURE 7-48: VC RESOURCE CAPABILITYREGISTER.................................................................. 517 FIGURE 7-49: VC RESOURCE CONTROL REGISTER...................................................................... 519 FIGURE 7-50: VC RESOURCE STATUS REGISTER......................................................................... 521 FIGURE 7-51: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 523 FIGURE 7-52: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES .......................................................................................................................................... ... 524 FIGURE 7-53: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 525 FIGURE 7-54: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER ................................. 526PCI EXPRESS BASE SPECIFICATION, REV. 2.0 14FIGURE 7-55: SERIAL NUMBER REGISTER................................................................................... 527 FIGURE 7-56: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 529 FIGURE 7-57: ROOT COMPLEX LINK DECLARATION ENHANCED CAPABILITY HEADER .............. 529 FIGURE 7-58: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 530 FIGURE 7-59: LINK ENTRY.......................................................................................................... 531 FIGURE 7-60: LINK DESCRIPTION REGISTER ............................................................................... 532 FIGURE 7-61: LINK ADDRESS FOR LINK TYPE 0 .......................................................................... 533 FIGURE 7-62: LINK ADDRESS FOR LINK TYPE 1 .......................................................................... 534 FIGURE 7-63: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 535 FIGURE 7-64: ROOT INTERNAL LINK CONTROL ENHANCED CAPABILITY HEADER ..................... 535 FIGURE 7-65: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 536 FIGURE 7-66: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 538 FIGURE 7-67: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 540 FIGURE 7-68: PCI EXPRESS POWER BUDGETING CAPABILITYSTRUCTURE................................. 541 FIGURE 7-69: POWER BUDGETING ENHANCED CAPABILITY HEADER ......................................... 541 FIGURE 7-70: POWER BUDGETING DATA REGISTER.................................................................... 543 FIGURE 7-71: POWER BUDGET CAPABILITY REGISTER ............................................................... 545 FIGURE 7-72: ACS EXTENDED CAPABILITY................................................................................ 545 FIGURE 7-73: ACS EXTENDED CAPABILITY HEADER ................................................................. 546 FIGURE 7-74: ACS CAPABILITY REGISTER................................................................................. 546 FIGURE 7-75: ACS CONTROL REGISTER .................................................................................... 548 FIGURE 7-76: EGRESS CONTROL VECTOR REGISTER................................................................... 550 FIGURE 7-77: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 551 FIGURE 7-78: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION ENHANCED CAPABILITY HEADER........................................................................................................... 551 FIGURE 7-79: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 553 FIGURE 7-80: MFVC ENHANCED CAPABILITY HEADER ............................................................. 553 FIGURE 7-81: PORT VC CAPABILITY REGISTER 1 ....................................................................... 554 FIGURE 7-82: PORT VC CAPABILITY REGISTER 2 ....................................................................... 556 FIGURE 7-83: PORT VC CONTROL REGISTER .............................................................................. 557 FIGURE 7-84: PORT VC STATUS REGISTER ................................................................................. 558 FIGURE 7-85: VC RESOURCE CAPABILITY REGISTER.................................................................. 558 FIGURE 7-86: VC RESOURCE CONTROL REGISTER...................................................................... 560 FIGURE 7-87: VC RESOURCE STATUS REGISTER......................................................................... 562 FIGURE 7-88: PCI EXPRESS VSEC STRUCTURE .......................................................................... 565 FIGURE 7-89: VENDOR-SPECIFIC ENHANCED CAPABILITY HEADER............................................ 566FIGURE 7-90: VENDOR-SPECIFIC HEADER .................................................................................. 567 FIGURE 7-91: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 568 FIGURE 7-92: RCRB HEADER ENHANCED CAPABILITY HEADER................................................ 568 FIGURE 7-93: VENDOR ID AND DEVICE ID ................................................................................. 569 FIGURE 7-94: RCRB CAPABILITIES ............................................................................................ 570 FIGURE 7-95: RCRB CONTROL................................................................................................... 570 FIGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER COMMUNICATION MODELS.................................................................................................. 572 FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTIONANDCONGESTION..................................................................................................................... ... 573PCI EXPRESS BASE SPECIFICATION, REV. 2.0 15FIGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS .......................................................................................................................................... ... 578 FIGURE C-1: SCRAMBLING SPECTRUM FOR DATA VALUE OF 0 ................................................... 597PCI EXPRESS BASE SPECIFICATION, REV. 2.0 16TablesTABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 48 TABLE 2-2: FMT[1:0] FIELD VALUES ............................................................................................ 52 TABLE 2-3: FMT[1:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 53 TABLE 2-4: LENGTH[9:0] FIELD ENCODING..........