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高速模数转换器(ADC)的INL/DNL测量
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作者：佚名日 09:40
[导读] 高速模数转换器(ADC)的INL/DNL测量
Abstract: Although integral and differential nonlinearity may not be the most important parameters for high-speed, high dynamic performance data converters, they gain significan
高速模数转换器(ADC)的INL/DNL测量
Abstract: Although integral and differential nonlinearity may not be the most important parameters for high-speed, high dynamic performance data converters, they gain significance when it comes to high-resolution imaging applications. The following application note serves as a refresher course for their definitions and details two different, yet commonly used techniques to measure INL and DNL in high-speed analog-to-digital converters (ADCs). Manufacturers have recently introduced high-performance analog-to-digital converters (ADCs) that feature outstanding static and dynamic performance. You might ask, "How do they measure this performance, and what equipment is used?" The following discussion should shed some light on techniques for testing two of the accuracy parameters important for ADCs: integral nonlinearity (INL) and differential nonlinearity (DNL). Although INL and DNL are not among the most important electrical characteristics that specify the high-performance data converters used in communications and fast data-acquisition applications, they gain significance in the higher-resolution imaging applications. However, unless you work with ADCs on a regular basis, you can easily forget the exact definitions and importance of these parameters. The next section therefore serves as a brief refresher course.
INL and DNL Definitions
DNL error is defined as the difference between an actual step width and the ideal value of 1LSB (see Figure 1a). For an ideal ADC, in which the differential nonlinearity coincides with DNL = 0LSB, each analog step equals 1LSB (1LSB = VFSR/2N, where VFSR is the full-scale range and N is the resolution of the ADC) and the transition values are spaced exactly 1LSB apart. A DNL error specification of less than or equal to 1LSB guarantees a monotonic transfer function with no missing codes. An ADC's monotonicity is guaranteed when its digital output increases (or remains constant) with an increasing input signal, thereby avoiding sign changes in the slope of the transfer curve. DNL is specified after the static gain error has been removed. It is defined as follows:
DNL = |[(VD+1- VD)/VLSB-IDEAL - 1] | , where 0 & D & 2N - 2.
VD is the physical value corresponding to the digital output code D, N is the ADC resolution, and VLSB-IDEAL is the ideal spacing for two adjacent digital codes. By adding noise and spurious components beyond the effects of quantization, higher values of DNL usually limit the ADC's performance in terms of signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR).Figure 1a. To guarantee no missing codes and a monotonic transfer function, an ADC's DNL must be less than 1LSB.INL error is described as the deviation, in LSB or percent of full-scale range (FSR), of an actual transfer function from a straight line. The INL-error magnitude then depends directly on the position chosen for this straight line. At least two definitions are common: "best straight-line INL" and "end-point INL" (see Figure 1b):
Best straight-line INL provides information about offset (intercept) and gain (slope) error, plus the position of the transfer function (discussed below). It determines, in the form of a straight line, the closest approximation to the ADC's actual transfer function. The exact position of the line is not clearly defined, but this approach yields the best repeatability, and it serves as a true representation of linearity.
End-point INL passes the straight line through end points of the converter's transfer function, thereby defining a precise position for the line. Thus, the straight line for an N-bit ADC is defined by its zero (all zeros) and its full-scale (all ones) outputs.
The best straight-line approach is generally preferred, because it produces better results. The INL specification is measured after both static offset and gain errors have been nullified, and can be described as follows:
INL = | [(VD - VZERO)/VLSB-IDEAL] - D | , where 0 & D & 2N-1.
VD is the analog value represented by the digital output code D, N is the ADC's resolution, VZERO is the minimum analog input corresponding to an all-zero output code, and VLSB-IDEAL is the ideal spacing for two adjacent output codes.Figure 1b. Best straight-line and end-point fit are two possible ways to define the linearity characteristic of an ADC.Transfer FunctionThe transfer function for an ideal ADC is a staircase in which each tread represents a particular digital output code and each riser represents a transition between adjacent codes. The input voltages corresponding to these transitions must be located to specify many of an ADC's performance parameters. This chore can be complicated, especially for the noisy transitions found in high-speed converters and for digital codes that are near the final result and changing slowly.Transitions are not sharply defined, as shown in Figure 1b, but are more realistically presented as a probability function. As the slowly increasing input voltage passes through a transition, the ADC converts more and more frequently to the next adjacent code. By definition, the transition corresponds to that input voltage for which the ADC converts with equal probability to each of the flanking codes.The Right Transition A transition voltage is defined as the input voltage that has equal probabilities of generating either of the two adjacent codes. The nominal analog value, corresponding to the digital output code generated by an analog input in the range between a pair of adjacent transitions, is defined as the midpoint (50% point) of this range. If the limits of the transition interval are known, this 50% point is calculated easily. The transition point can be determined at test by measuring the limits of the transition interval, and then dividing the interval by the number of times each of the adjacent codes appears within it.
Generic Setup for Testing Static INL and DNL
INL and DNL can be measured with either a quasi-DC voltage ramp or a low-frequency sine wave as the input. A simple DC (ramp) test can incorporate a logic analyzer, a high-accuracy DAC (optional), a high-precision DC source for sweeping the input range of the device under test (DUT), and a control interface to a nearby PC or X-Y plotter.If the setup includes a high-accuracy DAC (much higher than that of the DUT), the logic analyzer can monitor offset and gain errors by processing the ADC's output data directly. The precision signal source creates test voltages for the DUT by sweeping slowly through the input range of the ADC from zero scale to full scale. Once reconstructed by the DAC, each test voltage at the ADC input is subtracted from its corresponding DC level at the DAC output, producing a small voltage difference (VDIFF) that can be displayed with an X-Y plotter and linked to the INL and DNL errors. A change in quantization level indicates differential nonlinearity, and a deviation of VDIFF from zero indicates the presence of integral nonlinearity.
Analog Integrating Servo Loop
Another way to determine static linearity parameters for an ADC, similar to the preceding but more sophisticated, is using an analog integrating servo loop. This method is usually reserved for test setups that focus on high-precision measurements rather than speed.A typical analog servo loop (see Figure 2) consists of an integrator and two current sources connected to the ADC input. One source forces a current into the integrator, and the other serves as a current sink. A digital magnitude comparator connected to the ADC output controls both current sources. The other input of the magnitude comparator is controlled by a PC, which sweeps it through the 2N - 1 test codes for an N-bit converter.Figure 2. This circuit configuration is an analog integrating servo loop.If the polarity of feedback around the loop is correct, the magnitude comparator causes the current sources to servo the analog input around a given code transition. Ideally, this action produces a small triangular wave at the analog inputs. The magnitude comparator controls both rate and direction for these ramps. The integrator's ramp rate must be fast when approaching a transition, yet sufficiently slow to minimize peak excursions of the superimposed triangular wave when measuring with a precision digital voltmeter (DVM).For INL/DNL tests on the MAX108, the servo-loop board connects to the evaluation board through two headers (see Figure 3). One header establishes a connection between the MAX108's primary (or auxiliary) output port and the magnitude comparator's latchable input port (P). The second header ensures a connection between the servo loop (the magnitude comparator's Q port) and a computer-generated digital reference code.Figure 3. With the aid of the MAX108EVKIT and an analog integrating servo loop, this test setup determines the MAX108's INL and DNL characteristics.The fully decoded decision resulting from this comparison is available at the comparator output P & QOUT, and is then passed on to the integrator configurations. Each comparator result controls the logic input of the switch independently and generates voltage ramps as required to drive succeeding integrator circuits for both inputs of the DUT. This approach has its advantages, but it also has several drawbacks:
The triangular ramp should have low dV/dt to minimize noise. This condition generates repeatable numbers, but it results in long integration times for the precision meter.
Positive and negative ramp rates must be matched to arrive at the 50% point, and the low-level triangular waves must be averaged to achieve the desired DC level.
Integrator designs usually require careful selection of the charge capacitors. To minimize potential errors due to the capacitors' "memory effect," for instance, select integrator capacitors with low dielectric absorption.
Accuracy is proportional to the integration period and inversely proportional to the settling time.
A DVM connected to the analog integrated servo loop measures the INL/DNL error versus output code (Figures 4a and 4b). Note that a parabolic or bow shape in the plot of "INL vs. output code" indicates the predominance of even-order harmonics, and an "S shape" indicates the predominance of odd-order harmonics.Figure 4a. This plot shows typical integral nonlinearity for the MAX108 ADC, captured with the analog integrating servo loop.Figure 4b. This plot shows typical differential nonlinearity for the MAX108, captured with the analog integrating servo loop.To eliminate negative effects in the previous approach, you can replace the servo loop's integrator section with an L-bit successive-approximation register (SAR) that captures the DUT's output codes, an L-bit DAC, and a simple averaging circuit. Together with the magnitude comparator, this circuit forms a SAR-type converter configuration (see Figure 5 and "SAR Converter" discussion below), in which the magnitude comparator programs the DAC, reads its outputs, and performs a successive approximation. Meanwhile, the DAC presents a high-resolution DC level to the input of the N-bit ADC under test. In this case, a 16-bit DAC was chosen to trim the ADC to 1/8LSB accuracy and obtain the best possible transfer curve.Figure 5. Successive approximation and a DAC configuration replace the integrator section of the analog servo loop.The advantage of an averaging circuit is apparent when noise causes the magnitude comparator to toggle and become unstable, as it does on approaching its final result. Two divide-by counters are included in the averaging circuit. The "reference" counter has a period of 2M clock cycles, where M is a programmable integer governing the period (and hence the test time). A "data" counter, which increments only when the magnitude comparator output is high, has a period equal to one-half of the first 2M-1 cycles.Together, the reference and data counters average the number of highs and lows, store the result in a flip-flop, and pass it on to the SAR register. This procedure is repeated 16 times (in this case) to generate the complete output code word. Like the previous method, this one has advantages and disadvantages:
The test setup's input voltage is defined digitally, allowing easy modification of the number of samples over which the result is to be averaged.
The SAR approach provides a DC level rather than a ramp at the DUT's analog input.
As a disadvantage, the DAC in the feedback loop sets a finite limit on resolution of the input voltage.
SAR ConverterA SAR converter works like the old-fashioned chemist's balance. On one side is the unknown input sample, and on the other is the first weight generated by the SAR/DAC configuration (the most significant bit, which equals half of the full-scale output). If the unknown weight is larger than 1/2FSR, this first weight remains on the balance and is augmented by 1/4FSR. If the unknown weight is smaller, the weight is removed and replaced by a weight of 1/4FSR.The SAR converter then determines the desired output code by repeating this procedure N times, progressing from the MSB to the LSB. N is the resolution of the DAC in the SAR configuration, and each weight represents 1 binary bit.
Dynamic Testing of INL and DNL
To assess an ADC's dynamic nonlinearity, you can apply a full-scale sinusoidal input and measure the converter's signal-to-noise ratio (SNR) over its entire full-power input bandwidth. The theoretical SNR for an ideal N-bit converter (subject only to quantization noise, with no distortion) is as follows:
SNR (in dB) = N×6.02 +1.76.
Embedded in this figure of merit are the effects of glitches, integral nonlinearity, and sampling-time uncertainty. You can obtain additional linearity information by performing the SNR measurement at a constant frequency and as a function of the signal amplitude. Sweeping the entire amplitude range, for example, from zero to full scale and vice versa, produces large deviations from the source signal, as source amplitude approaches the converter's full-scale limit. To determine the cause of these deviations, while ruling out the effects of distortion and clock instability, use a spectrum analyzer to analyze the quantization-error signal as a function of frequency.Countless other approaches are available for testing the static and dynamic INL and DNL of both high- and low-speed data converters. The intent here has been to give you a better understanding of the generation of powerful TOCs (typical operating characteristics) using tools and techniques that are simple but still smart and precise.References
MAX108 data sheet, Rev. 1, 5/99, Maxim Integrated Products.
MAX108EVKIT data sheet, Rev. 0, 6/99, Maxim Integrated Products.
Analog Integrated Circuit Design, D. Johns & K. Martin, John Wiley & Sons Inc., 1997.
Low-Voltage/Low-Power Integrated Circuits and Systems, Low-Voltage Mixed-Signal Circuits, E. Sanchez-Sinencio & A. G. Andreou, IEEE Press Marketing, 1999.
Integrated Analog-to-Digital and Digital-to-Analog Converters, R. van de Plasche, Kluwer Academic Publishers, 1994.
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ADC测试中INL与THD之间的关系
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&&随着ADC测试技术的不断发展,码密度直方图技术以及采用正弦波输入的离散傅里叶变换(DFT)频域分析技术已经被广泛应用到ADC的仿真和测试分析中。相对于采用DFT进行频域分析获取ADC的动态性能的复杂性来说,采用码密度直方图的方法能简单地得到微分非线性(DNL)和积分非线性(INL)这两个静态性能指标。文章通过对一个10位ADC的行为级模型的仿真分析,阐述了总谐波失真(THD)与INL
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请填写真实有效的信息，以便工作人员联系您，我们为您严格保密。&&&&& 笔者最近在做的一个项目中，用到一片16位的高分辨率的芯片，借此再学习一下由于ADC和DAC的相关知识，以此巩固。
&&&&& 关于ADC的精度和分辨率将在另外一篇博客讨论，分辨率不等于精度。
&&&& 一块精度0.2%（或常说的准确度0.2级）的四位半万用表，测得A点电压1.0000V，B电压1.0005V,可以分出B比A高0.0005V，但A点电压的真实值可能在0.0之间不确定。
&&&&&& 那么,既然数字万用表存在着精度和分辨率两个指标，那么,对于ADC和DAC，除了分辨率以外，也存在精度的指标。模数器件的精度指标是用积分非线性度（Interger NonLiner）即INL值来表示。也有的器件手册用 Linearity error 来表示。他表示了ADC器件在所有的数值点上对应的模拟值，和真实值之间误差最大的那一点的误差值。也就是，输出数值偏离线性最大的距离。单位是LSB（即最低位所表示的量）。
&&&&&& 比如12位ADC：TLC2543，INL值为1LSB。那么，如果基准4.095V，给定数字量1000，输出电压在1V，那么，真实电压值可能分布在0.999~1.001V之间。对于DAC也是类似的。比如DAC7512,INL值为8LSB，那么，如果基准4.095V，给定数字量1000，那么输出电压可能是0.992~1.008V之间。
&&&&& 下面再说DNL值。理论上说，模数器件相邻量个数据之间，模拟量的差值都是一样的。就相一把疏密均匀的尺子。但实际并不如此。一把分辨率1毫米的尺子，相邻两刻度之间也不可能都是1毫米整。那么，ADC相邻两刻度之间最大的差异就叫差分非线性值（Differencial NonLiner）。DNL值如果大于1，那么这个ADC甚至不能保证是单调的，输入电压增大，在某个点数值反而会减小。这种现象在SAR（逐位比较）型ADC中很常见。 &&&& 举个例子，某12位ADC，INL=8LSB，DNL=3LSB（性能比较差），基准4.095V，测A电压读数1000，测B电压度数1200。那么，可判断B点电压比A点高197~203mV。而不是准确的200mV。对于DAC也是一样的，某DAC的DNL值3LSB。那么，如果数字量增加200，实际电压增加量可能在197~203mV之间。
&&&&& 很多分辨率相同的ADC，价格却相差很多。除了速度、温度等级等原因之外，就是INL、DNL这两个值的差异了。比如AD574,贵得很，但它的INL值就能做到0.5LSB，这在SAR型ADC中已经很不容易了。换个便宜的2543吧，速度和分辨率都一样，但INL值只有1~1.5LSB，精度下降了3倍。
&&&& 另外，工艺和原理也决定了精度。比如SAR型ADC，由于采用了R-2R或C-2C型结构，使得高权值电阻的一点点误差，将造成末位好几位的误差。在SAR型ADC的2^n点附近，比如128、、切换权值点阻，误差是最大的。1024值对应的电压甚至可能会比1023值对应电压要小。这就是很多SAR型器件DNL值会超过1的原因。但SAR型ADC的INL值都很小，因为权值电阻的误差不会累加。
和SAR型器件完全相反的是阶梯电阻型模数/数模器件。比如TLC5510、DAC7512等低价模数器件。比如7512，它由4095个电阻串联而成。每个点阻都会有误差，一般电阻误差5%左右，当然不会离谱到100%，更不可能出现负数。因此这类器件的DNL值都很小,保证单调。但是，每个电阻的误差，串联后会累加，因此INL值很大，线性度差。
&&&& 这里要提一下双积分ADC，它的原理就能保证线性。比如ICL7135，它在40000字的量程内，能做0.5LSB的INL值（线性度达到1/80000 !!）和0.01LSB的DNL值.这两个指标在7135的10倍价钱内，是不容易被其他模数器件超越的。所以7135这一类双积分ADC特别适合用在数字电压表等需要线性误差非常小的场合。
&&&& 还要特别提一下基准源。基准源是测量精度的重要保证。基准的关键指标是温飘，一般用ppm/K来表示。假设某基准30ppm/K，系统在20~70度之间工作，温度跨度50度，那么，会引起基准电压30*50=1500ppm的漂移，从而带来0.15%的误差。温漂越小的基准源越贵，比如30ppm/K的431，七毛钱；20ppm/K的385，1块5；10ppm/K的MC；1ppm/K的LM399,14元；0.5ppm/K的LM199，130元。
该死的教科书害了一代学生。在ADC电路中的基准源不能直接接电源VCC，这里要考虑基准电压的稳定度。其中常用的基准源电压可由TL431提供。
&&&&&& 最后说一下Sigma-Delta型ADC，它比较特殊，对于精度，一般用直接用线性度表示，比如0.0015%.不说差分非线性值，而直接用有效分辨率来表示。此外，Sigma-Delta型ADC还存许多怪脾气，难伺候。
&&&& （1）INL(Interger NonLinear,Linearity error)精度。理解为单值数据误差，对应该点模拟数据由于元器件及结构造成的不能精确测量产生的误差。
&&&& （2）DNL(Differential NonLinear)差分非线性值。理解为刻度间的差值，即对每个模拟数据按点量化，由于量化产生的误差。
&&&& (1)INL,精度
&&&& 比如12位ADC：假设基准Vref=4.095V,那么1LSB=Vref/2^12=0.001V。如果精度为1LSB，则它的单值测量误差0.001V*1=0.001V,比如测量结果1.000V，实际在1.000+/-0.001V范围。如果精度为8LSB，则他的单值测量误差0.001V*8=0.008V,比如测量结果1.000V，实际在1.000+/-0.008V范围
(2)DNL，差分非线性值
&&&& 比如12位ADC：假设基准Vref=4.095V,那么1LSB=Vref/2^12=0.001V。不考虑精度，即精度为0LSB。没有单值误差。如果DNL=3LSB=0.001V*3=0.003V假设A实际电压为1.001V,B实际电压为1.003V。理论上A点读数1.001V/1LSB=1001，B点读数1.003V/1LSB=1003，B-A=2,B&A，但由DNL=3LSB=0.003V,模拟数据间的量化误差有0.003V，那么B-A会在-1(2-3=-1)到+5(2+3=5)之间的某一个数。
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