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STM32F103VET6最小系统板原理图
1 *1 C1 10 C2 10 C3 20 C4 PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13 7 PC14 8 PC15 9 10 3.3V 11 12 13 NRST 14 PC0 15 PC1 16 PC2 17 PC3 18 19 VREF- 20 VREF+ 21 3.3V 22 PA0 23 PA1 24 PA2 25 PA3 26 27 3.3V 28 PA4 29 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 PB11 48 49 3.3V 502345632.768k 2 Y1 1AGNDGND 8M 2 Y2 1GNDGNDBGNDS1 GND 3.3V 104 C5 R1 10K NRST3.3V C C9 104 C10 104 C11 104 C12 104GNDPE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0/ADC123_IN10 PC1/ADC123_IN11 PC2/ADC123_IN12 PC3/ADC123_IN13 VSSA VREFVREF+ VDDA PA0/ADC123_IN0 PA1/ADC123_IN1 PA2/ADC123_IN2 PA3/ADC123_IN3 VSS_4 VDD_4 PA4/ADC12_IN4 PA5/ADC12_IN5 PA6/ADC12_IN6 PA7/ADC12_IN7 PC4/ADC12_IN14 PC5/ADC12_IN15 PB0/ADC12_IN8 PB1/ADC12_IN9 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10/USART3_TX PB11/USART3_RX VSS_1 VDD_1 STM32F103VXT6PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8/USART1_CK/TIM1_CH2 PA9/USART1_TX PA10/USART1_RX PA11 PA12 PA13/JTMS/SWDIO NC VSS_2 VDD_2 PA14/JTCK/SWCLK PA15/JTDI PC10/UART4_TX PC11/UART4_RX PC12/UART5_TX PD0 PD1 PD2/UART5_RX PD3 PD4 PD5 PD6 PD7 PB3/JTDO PB4/JNTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_351 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13 3.3V PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 3.3V GND GNDP1 PA14 1 PC10 3 PC12 5 PD1 7 PD3 9 PD5 11 PD7 13 PB4 15 PB6 17 BOOT0 19 PB9 21 PE1 23 PE3 25 PE5 27 VBAT 292 4 6 8 10 12 14 16 18 20 22 24 26 28 30PA15 PC11 PD0 PD2 PD4 PD6 PB3 PB5 PB7 PB8 PE0 PE2 PE4 PE6 PC13P2 PC15 1 PC0 3 PC2 5 VREF7 PA0 9 PA2 11 PA4 13 PA6 15 PC4 17 PB0 19 PB2 21 PE8 23 PE10 25 PE12 27 PE14 292 4 6 8 10 12 14 16 18 20 22 24 26 28 30PC14 NRST PC1 PC3 VREF+ PA1 PA3 PA5 PA7 PC5 PB1 PE7 PE9 PE11 PE13P3 PB10 1 PB12 3 PB14 5 PD8 7 PD10 9 PD12 11 PD14 13 PC6 15 PC8 17 PA8 19 PA10 21 PA12 23 25 5V 27 3.3V 292 4 6 8 10 12 14 16 18 20 22 24 26 28 30PE15 PB11 PB13 PB15 PD9 PD11 PD13 PD15 PC7 PC9 PA9 PA11 PA13 GND GNDAHeader 15X2Header 15X2Header 15X23.3V B R9 R10 R11 R12 R13 10K 10k 10k 10k 10k JTAG1 PB4 PA15 PA13 PA14 PB3 NRST 1 3 5 7 9 11 13 15 17 19 Vref Vsupply nTRST GND1 TDI GND2 TMS GND3 TCK GND4 RTCK GND5 TDO GND6 nSRST GND7 DBGRQ GND8 DBGACK GND9 2 4 6 8 10 12 14 16 18 20 GND C 3.3V R5 330 USB--BB1 5V 1 2 3 4 5 R6 5V 22 22 3.3V PA11 PA12 3 1 U2 IN OUT GND OUT REG GND 2 4 3.3V C6 104 C7 104 GND D2JTAG5VGNDR7 R8 1.5k GNDD1 3.3V R2 430 PB0 3.3V GND P4 D PA0 R4 S2 GND 10K 3.3V R17 10K PB2 1 3 2 4 R16 10K BOOT0 SPI1 NSS SPI1 MISO 3.3V PA4 1 PA6 2 3 4 GND 3.3VFLASHU4 CS VCC Q HOLD W C GND D 2M FLASH 8 7 6 5 3.3V PA5 PA7 Title Size A4 Date: File: Number 139SR 郝袅人
D:\139晟睿电子\..\Sheet1.SchDoc 5 Sheet of Drawn By: 6 Revision DSPI1 SCK SPI1 MOSI1234
基于STM32F103ZET6最小系统设计_信息与通信_工程...图 的方法,自己 构造印制板元件库; 7.了解电路板...4.绘制主要模块 (1)CPU 模块--STM32F103VET6(...本文主要介绍了以 PCB 板制作 STM32F103 最小系统电路板的基本过程,以 及制作的整体思路和在制作的过程应注意的地方,本 PCB 板涉及到了元件原理 图绘制、 元件...STM32F103C8T6最小系统电路原理图_电子/电路_工程科技_专业资料 暂无评价|0人阅读|0次下载|举报文档STM32F103C8T6最小系统电路原理图_电子/电路_工程科技_专业...STM32F103最小化系统电路_电子/电路_工程科技_专业资料。STM32F103最小化系统电路,适合初学者。下图是主控芯片 STM32F103 的最小化系统,包括时钟电路、复位电路、...YL-29 STM32F103Zx最小系统板使用说明_IT/计算机_专业资料。YL- STM32F103Zx...6、所有IO 和3.3V 电源接口均引出,方便接外部电路做实验 7、外扩2 路5V,GND...TM32F103ZET6 最小系统设计 【摘要】STM32F103ZET6 是意法半导体公司基于 ...一、原理图设计 一个最小的核心板原理图分为电源供电,外部时钟,启动方式,复位...以STM32F103RDT6为控制系统的单片机最小系统_电子/电路_工程科技_专业资料。以...中规模应用电路“STM32F746IGT6 为主控芯片的核心板”的项目原理 图及 PCB ...《电路设计与 PCB 制板》 设计报告题 目: 基于 STM32F103 最小系统的 232 ...的封装; 5、导入 PCB 图进行绘制及布线; 6、进入 DRC 检查; 三、原理图...STM32 带can通讯 485 串口 232串口通讯 中文件资料 最小系统说明书_信息与通信_工程科技_专业资料。此文档主要为STM32F103C8T6芯片的最小系统板原理图解析,以及...
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STM32F4究竟能不能2.4M采集ADC
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先不考虑精度问题，以及多ADC模块交替采集提高采样率的方法，
单ADC模块最高速也只有2.4M，就算开了DMA，
那么，应该也要等DMA搬走ADC值寄存器里的数据后，ADC模块才能填装ADC值寄存器，这样就拖慢了，
还有，用软件或DMA断断续续地搬1字节，究竟谁快？（不用考虑拖慢其它功能代码的问题）
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速度由外设决定，但DMA可以做到接近0延时。
且使用DMA时，CPU可以去做别的，比如示波器的UI显示和数据处理。
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f4应该做不到这么快吧。
多通道交叉采样也不错；
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aozima 发表于
速度由外设决定，但DMA可以做到接近0延时。
且使用DMA时，CPU可以去做别的，比如示波器的UI显示和数据处理 ...
只要高速采集ADC值，不用考虑占用CPU的问题，
DMA速度应该也是由系统时钟决定，
所以问软件搬数据还是DMA搬数据快？
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hanzhen654 发表于
f4应该做不到这么快吧。
也有可能行，DMA利用ADC采样时的3个时钟搬出ADC值寄存器的数据，
只不过这么小的时间不好测试是否靠谱
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mmuuss586 发表于
多通道交叉采样也不错；
不考虑多ADC模块交替采集提高采样率的方法
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F4可以到2.4MSps的，我用F407 AD采样带DMA，然后FFT，按照2.4M采样速率计算信号频率，与实际输入信号频率是一致的
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速度由外设决定，但DMA可以做到接近0延时。
且使用DMA时，CPU可以去做别的，比如示波器的UI显示和数据处理 ...
初级工程师, 积分 2468, 距离下一级还需 532 积分
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ADC一次转换时间最小为3+12 = 15个时钟周期，最大为480+12 = 492个时钟周期。ADC的一个时钟周期计算如下：APB2频率 / ADC分频，举个例子，如果APB2时钟为 84MHz，ADC分频为2分频，那么ADC的频率为42MHz，一个时钟周期为0.023us, 因此最小转换时间为 15时钟周期*1us = 0.345us(2.9MHz)， 最大492us（88.5KHz）。
不考虑多ADC模块交替采集提高采样率的方法
那最快只能这么快，实际还要打一些折扣；
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差不多可以的，3个周期的采样周期，满频跑，采集端加个跟随，数值没问题
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对的，需要加跟随
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采集端加跟随是什么目的呢？？
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也有可能行，DMA利用ADC采样时的3个时钟搬出ADC值寄存器的数据，
只不过这么小的时间不好测试是否靠谱 ...
那你试一下，多尝试几次，不行用F7试试。
F3速度5M的飘过， 显然是DMA一次采集指定长度，比如10K，不能无限采集是因为没法实时处理或者传出去(F4有高速USB，可以实时传出去，也就可以无限采集).& && & DMA会占总线带宽，你2.4M假设毛估占3M,你单片机运行假设50M(难道你买个F4只运行10M?),&&才占了 3/50=6%. CPU占用约等于0。
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三重采样很简单,就是三个ADC叠加成更高速度,但是不是所有通道都支持三重采样.如图,只有写着ADC123_INx的才可以.
当初改掉原来官方的ADC1 + ADC2接PA4结果什么用都没,真是麻烦.另外只能按照WORD传输.进入DMA中断后要赶紧处理数据.取出高16和低16位.这个三重下,顺序是比较复杂(其实也就是先来后到),不过实际上不用管,当做只有一个ADC在工作就好了.
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
aADCyMultimodeDualSlaveConvertedData[tmp_index]
= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
&&&&&&&&aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);&&&&&&&&aADCyMultimodeDualSlaveConvertedData[tmp_index]&&= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
得到数据该怎么处理就怎么处理,这么快速度,串口是发不走的了,因为串口至少得bps,不太可能,看看怎么送出去了,这数据.或者处理.
******************************************************************************
Examples_LL/ADC/ADC_MultimodeDualInterleaved/Src/main.c
MCD Application Team
* @version V1.0.0
30-December-2016
This example describes how to use several ADC peripherals in
multimode, mode interleaved.
ADC master instance synchronizes and manages ADC slave instance.
Multimode interleaved combines ADC instances to convert
the same channel and increase the overall ADC conversion rate.
This example configures the ADC to perform conversions at the
maximum ADC conversion rate possible (with a sampling time
corresponding to ADC resolution 12 bits).
This example is based on the STM32F7xx ADC LL API;
Peripheral initialization done using LL unitary services functions.
******************************************************************************
* @attention
* &h2&&center&(C) COPYRIGHT(c) 2016 STMicroelectronics&/center&&/h2&
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of STMicroelectronics nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/** @addtogroup STM32F7xx_LL_Examples
/** @addtogroup ADC_MultimodeDualInterleaved
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Definitions of ADC hardware constraints delays */
/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,
not timeout values:
Timeout values for ADC operations are dependent to device clock
configuration (system clock versus ADC clock),
and therefore must be defined in user application.
Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout
values definition.
/* Timeout values for ADC operations. */
/* (enable settling time, disable settling time, ...)
/* Values defined to be higher than worst cases: low clock frequency,
/* maximum prescalers.
/* Example of profile very low frequency : ADC clock frequency 36MHz
/* prescaler 2, sampling time 56 ADC clock cycles, resolution 12 bits.
- ADC enable time: maximum delay is 3 us
(refer to device datasheet, parameter "tSTAB")
- ADC disable time: maximum delay should be a few ADC clock cycles
- ADC stop conversion time: maximum delay should be a few ADC clock
- ADC conversion time: with this hypothesis of clock settings, maximum
delay will be 99us.
(refer to device reference manual, section "Timing")
/* Unit: ms
#define ADC_CALIBRATION_TIMEOUT_MS
((uint32_t)
#define ADC_ENABLE_TIMEOUT_MS
((uint32_t)
#define ADC_DISABLE_TIMEOUT_MS
((uint32_t)
#define ADC_STOP_CONVERSION_TIMEOUT_MS
((uint32_t)
#define ADC_CONVERSION_TIMEOUT_MS
((uint32_t)
/* Definitions of environment analog values */
/* Value of analog reference voltage (Vref+), connected to analog voltage
/* supply Vdda (unit: mV).
#define VDDA_APPLI
((uint32_t)3300)
/* Definitions of data related to this example */
/* Init variable out of expected ADC conversion data range */
#define VAR_CONVERTED_DATA_INIT_VALUE
(__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
/* Definition of ADCx conversions data table size */
/* Note: Considering interruption occurring after each number of
"ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions
(IT from DMA transfer complete),
select sampling time and ADC clock with sufficient
duration to not create an overhead situation in IRQHandler.
#define ADC_CONVERTED_DATA_BUFFER_SIZE
((uint32_t) 256)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Variables for ADC conversion data */
uint32_t aADCxADCyMultimodeDualConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];
/* ADC multimode dual conversion data: ADC master and ADC slave conversion data are concatenated in a registers of 32 bits. */
static uint16_t aADCxMultimodeDualMasterConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];/* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC master conversion data. */
static uint16_t aADCyMultimodeDualSlaveConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC slave conversion data. */
/* Variable to report status of DMA transfer of ADC group regular conversions */
0: DMA transfer is not completed
1: DMA transfer is completed
2: DMA transfer has not been started yet (initial state)
__IO uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback */
/* Private function prototypes -----------------------------------------------*/
SystemClock_Config(void);
Configure_DMA(void);
Configure_ADC(void);
Configure_ADC_slave(void);
Activate_ADC(void);
Activate_ADC_slave(void);
static void CPU_CACHE_Enable(void);
/* Private functions ---------------------------------------------------------*/
Main program
* @retval None
int main(void)
/* Enable the CPU Cache */
CPU_CACHE_Enable();
/* Configure the system clock to 216 MHz */
SystemClock_Config();
/* Initialize button in EXTI mode */
/* UserButton_Init(); */
/* Configure DMA for data transfer from ADC */
Configure_DMA();
/* Configure ADC */
/* Note: This function configures the ADC but does not enable it.
To enable it, use function "Activate_ADC()".
This is intended to optimize power consumption:
1. ADC configuration can be done once at the beginning
(ADC disabled, minimal power consumption)
2. ADC enable (higher power consumption) can be done just before
ADC conversions needed.
Then, possible to perform successive "Activate_ADC()",
"Deactivate_ADC()", ..., without having to set again
ADC configuration.
Configure_ADC();
/* For multimode, configure ADC slave */
Configure_ADC_slave();
/* Activate ADC */
/* Perform ADC activation procedure to make it ready to convert. */
Activate_ADC();
Activate_ADC_slave();
LL_ADC_REG_StartConversionSWStart(ADC1);
/* Infinite loop */
/* Note: ADC group regular conversion start is done into push button
IRQ handler, refer to function "UserButton_Callback()".
/* Note: LED state depending on DMA transfer status is set into DMA
IRQ handler, refer to functions "DmaTransferComplete()"
and "DmaTransferHalfComplete()".
/* Note: ADC conversion data are stored into array
"aADCxADCyMultimodeDualConvertedData".
For this example purpose, ADC conversion data of ADC master and
ADC slave are dispatched into arrays */
"aADCxMultimodeDualMasterConvertedData"
and "aADCyMultimodeDualSlaveConvertedData", refer to comments
into function "DmaTransferComplete()".
(for debug: see variable content into watch window).
/* Note: ADC conversion data can be computed to physical values
using ADC LL driver helper macro:
uhADCxConvertedData_Voltage_mVolt
= __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI,
uhADCxConvertedData),
LL_ADC_RESOLUTION_12B)
This function configures DMA for transfer of data from ADC
* @retval None
void Configure_DMA(void)
/*## Configuration of NVIC #################################################*/
/* Configure NVIC to enable DMA interruptions */
NVIC_SetPriority(DMA2_Stream0_IRQn, 1);
/* DMA IRQ lower priority than ADC IRQ */
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
/*## Configuration of DMA ##################################################*/
/* Enable the peripheral clock of DMA */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
/* Configure the DMA transfer */
- DMA transfer in circular mode to match with ADC configuration:
DMA unlimited requests.
- DMA transfer from ADC without address increment.
- DMA transfer to memory with address increment.
- DMA transfer from ADC by word to match with ADC configuration:
ADC resolution 12 bits and and multimode enabled,
ADC master and ADC slave conversion data are concatenated in
a register of 32 bits.
- DMA transfer to memory by word to match with ADC conversion data
buffer variable type: word.
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_0, LL_DMA_CHANNEL_0);
LL_DMA_ConfigTransfer(DMA2,
LL_DMA_STREAM_0,
LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
LL_DMA_MODE_CIRCULAR
LL_DMA_PERIPH_NOINCREMENT
LL_DMA_MEMORY_INCREMENT
LL_DMA_PDATAALIGN_WORD
LL_DMA_MDATAALIGN_WORD
LL_DMA_PRIORITY_HIGH
/* Set DMA transfer addresses of source and destination */
/* Note: On this STM32 device, in multimode, ADC conversion data with
ADC master and ADC slave conversion data concatenated are located
in a specific multimode data register.
LL_DMA_ConfigAddresses(DMA2,
LL_DMA_STREAM_0,
LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA_MULTI),
(uint32_t)&aADCxADCyMultimodeDualConvertedData,
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
/* Set DMA transfer size */
LL_DMA_SetDataLength(DMA2,
LL_DMA_STREAM_0,
ADC_CONVERTED_DATA_BUFFER_SIZE);
/* Enable DMA transfer interruption: transfer complete */
LL_DMA_EnableIT_TC(DMA2,
LL_DMA_STREAM_0);
/*## Activation of DMA #####################################################*/
/* Enable the DMA transfer */
LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_0);
Configure ADC (ADC instance: ADC1) and GPIO used by ADC channels.
In case re-use of this function outside of this example:
This function includes checks of ADC hardware constraints before
executing some configuration functions.
- In this example, all these checks are not necessary but are
implemented anyway to show the best practice usages
corresponding to reference manual procedure.
(On some STM32 series, setting of ADC features are not
conditioned to ADC state. However, in order to be compliant with
other STM32 series and to show the best practice usages,
ADC state is checked anyway with same constraints).
Software can be optimized by removing some of these checks,
if they are not relevant considering previous settings and actions
in user application.
- If ADC is not in the appropriate state to modify some parameters,
the setting of these parameters is bypassed without error
reporting:
it can be the expected behavior in case of recall of this
function to update only a few parameters (which update fullfills
the ADC state).
Otherwise, it is up to the user to set the appropriate error
reporting in user application.
Peripheral configuration is minimal configuration from reset values.
Thus, some useless LL unitary functions calls below are provided as
commented examples - setting is default configuration from reset.
* @retval None
void Configure_ADC(void)
/*## Configuration of GPIO used by ADC channels ############################*/
/* Note: On this STM32 device, ADC1 channel 4 is mapped on GPIO pin PA.04 */
/* Enable GPIO Clock */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
/* Configure GPIO in analog mode to be used as ADC input */
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);
/*## Configuration of ADC ##################################################*/
/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
/* Enable ADC clock (core clock) */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC clock (conversion clock) common to several ADC instances */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_CLOCK_SYNC_PCLK_DIV2);
/* Set ADC measurement path to internal channels */
// LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_NONE);
/*## Configuration of ADC hierarchical scope: multimode ####################*/
/* Set ADC multimode configuration */
LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TRIPLE_REG_INTERL);
/* Set ADC multimode DMA transfer */
LL_ADC_SetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_REG_DMA_UNLMT_3);
/* Set ADC multimode: delay between 2 sampling phases */
/* Note: Delay has been chosen to have ADC2 conversion start in the
mid-delay between ADC1 conversions.
LL_ADC_SetMultiTwoSamplingDelay(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES);
/*## Configuration of ADC hierarchical scope: ADC instance #################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC data resolution */
// LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B);
/* Set ADC conversion data alignment */
// LL_ADC_SetResolution(ADC1, LL_ADC_DATA_ALIGN_RIGHT);
/* Set Set ADC sequencers scan mode, for all ADC groups
/* (group regular, group injected).
// LL_ADC_SetSequencersScanMode(ADC1, LL_ADC_SEQ_SCAN_DISABLE);
/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Set ADC group regular trigger source */
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group regular trigger polarity */
// LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);
/* Set ADC group regular continuous mode */
LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_CONTINUOUS);
/* Set ADC group regular conversion data transfer */
/* Note: Both ADC master and ADC slave have multimode setting
to use 1 DMA channel for all ADC instances.
In this case, each ADC instance must have setting of
ADC DMA request set to default value (no DMA transfer).
and ADC DMA transfer is managed by ADC common instance.
Refer to function "LL_ADC_SetMultiDMATransfer()".
LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
/* Set ADC group regular sequencer */
/* Note: On this STM32 serie, ADC group regular sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_REG_SetSequencerLength()".
/* Set ADC group regular sequencer length and scan direction */
LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);
/* Set ADC group regular sequencer discontinuous mode */
// LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
/* Set ADC group regular sequence: channel on the selected sequence rank. */
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC group injected trigger source */
// LL_ADC_INJ_SetTriggerSource(ADC1, LL_ADC_INJ_TRIG_SOFTWARE);
/* Set ADC group injected trigger polarity */
// LL_ADC_INJ_SetTriggerEdge(ADC1, LL_ADC_INJ_TRIG_EXT_RISING);
/* Set ADC group injected conversion trigger
// LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
/* Set ADC group injected sequencer */
/* Note: On this STM32 serie, ADC group injected sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_INJ_SetSequencerLength()".
/* Set ADC group injected sequencer length and scan direction */
// LL_ADC_INJ_SetSequencerLength(ADC1, LL_ADC_INJ_SEQ_SCAN_DISABLE);
/* Set ADC group injected sequencer discontinuous mode */
// LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
/* Set ADC group injected sequence: channel on the selected sequence rank. */
// LL_ADC_INJ_SetSequencerRanks(ADC1, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: channels #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Set ADC channels sampling time */
/* Note: Considering interruption occurring after each number of
"ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions
(IT from DMA transfer complete),
select sampling time and ADC clock with sufficient
duration to not create an overhead situation in IRQHandler.
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_0, LL_ADC_SAMPLINGTIME_3CYCLES);
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
/* Note: On this STM32 serie, there is only 1 analog watchdog available.
/* Set ADC analog watchdog: channels to be monitored */
// LL_ADC_SetAnalogWDMonitChannels(ADC1, LL_ADC_AWD_DISABLE);
/* Set ADC analog watchdog: thresholds */
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
/*## Configuration of ADC transversal scope: oversampling ##################*/
/* Note: Feature not available on this STM32 serie */
/* Note: in this example, ADC group regular end of conversions
(number of ADC conversions defined by DMA buffer size)
are notified by DMA transfer interruptions).
For multimode, configure ADC slave (ADC instance: ADC2)
and GPIO used by ADC channels.
Configuration of GPIO:
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
Configuration of ADC:
- Common to several ADC:
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
- Multimode
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
In case re-use of this function outside of this example:
This function includes checks of ADC hardware constraints before
executing some configuration functions.
- In this example, all these checks are not necessary but are
implemented anyway to show the best practice usages
corresponding to reference manual procedure.
(On some STM32 series, setting of ADC features are not
conditioned to ADC state. However, in order to be compliant with
other STM32 series and to show the best practice usages,
ADC state is checked anyway with same constraints).
Software can be optimized by removing some of these checks,
if they are not relevant considering previous settings and actions
in user application.
- If ADC is not in the appropriate state to modify some parameters,
the setting of these parameters is bypassed without error
reporting:
it can be the expected behavior in case of recall of this
function to update only a few parameters (which update fullfills
the ADC state).
Otherwise, it is up to the user to set the appropriate error
reporting in user application.
Peripheral configuration is minimal configuration from reset values.
Thus, some useless LL unitary functions calls below are provided as
commented examples - setting is default configuration from reset.
* @retval None
void Configure_ADC_slave(void)
/*## Configuration of GPIO used by ADC channels ############################*/
/* Note: not configured: In this example, ADC slave group regular converts
the same channel as ADC master group regular.
Channel configuration same as ADC master.
/*## Configuration of ADC ##################################################*/
/* Enable ADC clock (core clock) */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC2);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC3);
/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
/* Note: ADC clock (core clock) not configured: same as ADC master
(ADC slave shares the common clock of ADC master).
/* Note: not configured: same as ADC master (ADC slave shares the common
configuration of ADC master).
/*## Configuration of ADC hierarchical scope: multimode ####################*/
/* Note: not configured: same as ADC master (ADC slave shares the common
configuration of ADC master).
/*## Configuration of ADC hierarchical scope: ADC instance #################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC data resolution */
// LL_ADC_SetResolution(ADC2, LL_ADC_RESOLUTION_12B);
/* Set ADC conversion data alignment */
// LL_ADC_SetResolution(ADC2, LL_ADC_DATA_ALIGN_RIGHT);
/* Set Set ADC sequencers scan mode, for all ADC groups
/* (group regular, group injected).
LL_ADC_SetSequencersScanMode(ADC2, LL_ADC_SEQ_SCAN_ENABLE);
LL_ADC_SetSequencersScanMode(ADC3, LL_ADC_SEQ_SCAN_ENABLE);
/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Set ADC group regular trigger source */
/* Note: On this STM32 device, in multimode, ADC slave trigger source
setting is mandatory: SW start.
LL_ADC_REG_SetTriggerSource(ADC2, LL_ADC_REG_TRIG_SOFTWARE);
LL_ADC_REG_SetTriggerSource(ADC3, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group regular continuous mode */
/* Note: On this STM32 device, in multimode, ADC slave continuous
conversions mode must be the same as ADC master.
LL_ADC_REG_SetContinuousMode(ADC2, LL_ADC_REG_CONV_CONTINUOUS);
LL_ADC_REG_SetContinuousMode(ADC3, LL_ADC_REG_CONV_CONTINUOUS);
/* Set ADC group regular conversion data transfer */
/* Note: Both ADC master and ADC slave have multimode setting
to use 1 DMA channel for all ADC instances.
In this case, each ADC instance must have setting of
ADC DMA request set to default value (no DMA transfer).
and ADC DMA transfer is managed by ADC common instance.
Refer to function "LL_ADC_SetMultiDMATransfer()".
LL_ADC_REG_SetDMATransfer(ADC2, LL_ADC_REG_DMA_TRANSFER_NONE);
LL_ADC_REG_SetDMATransfer(ADC3, LL_ADC_REG_DMA_TRANSFER_NONE);
/* Specify which ADC flag between EOC (end of unitary conversion)
/* or EOS (end of sequence conversions) is used to indicate
/* the end of conversion.
// LL_ADC_REG_SetFlagEndOfConversion(ADC2, LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV);
/* Set ADC group regular sequencer */
/* Note: On this STM32 serie, ADC group regular sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_REG_SetSequencerLength()".
/* Set ADC group regular sequencer length and scan direction */
LL_ADC_REG_SetSequencerLength(ADC2, LL_ADC_REG_SEQ_SCAN_DISABLE);
LL_ADC_REG_SetSequencerLength(ADC3, LL_ADC_REG_SEQ_SCAN_DISABLE);
/* Set ADC group regular sequencer discontinuous mode */
// LL_ADC_REG_SetSequencerDiscont(ADC2, LL_ADC_REG_SEQ_DISCONT_DISABLE);
/* Set ADC group regular sequence: channel on the selected sequence rank. */
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
LL_ADC_REG_SetSequencerRanks(ADC3, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC group injected trigger source */
// LL_ADC_INJ_SetTriggerSource(ADC2, LL_ADC_INJ_TRIG_SOFTWARE);
/* Set ADC group injected trigger polarity */
// LL_ADC_INJ_SetTriggerEdge(ADC2, LL_ADC_INJ_TRIG_EXT_RISING);
/* Set ADC group injected conversion trigger
// LL_ADC_INJ_SetTrigAuto(ADC2, LL_ADC_INJ_TRIG_INDEPENDENT);
/* Set ADC group injected sequencer */
/* Note: On this STM32 serie, ADC group injected sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_INJ_SetSequencerLength()".
/* Set ADC group injected sequencer length and scan direction */
// LL_ADC_INJ_SetSequencerLength(ADC2, LL_ADC_INJ_SEQ_SCAN_DISABLE);
/* Set ADC group injected sequencer discontinuous mode */
// LL_ADC_INJ_SetSequencerDiscont(ADC2, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
/* Set ADC group injected sequence: channel on the selected sequence rank. */
// LL_ADC_INJ_SetSequencerRanks(ADC2, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: channels #####################*/
/* Note: not configured: In this example, ADC slave group regular converts
the same channel as ADC master group regular.
Channel configuration same as ADC master.
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
/* Note: On this STM32 serie, there is only 1 analog watchdog available.
/* Set ADC analog watchdog: channels to be monitored */
// LL_ADC_SetAnalogWDMonitChannels(ADC2, LL_ADC_AWD_DISABLE);
/* Set ADC analog watchdog: thresholds */
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
/*## Configuration of ADC transversal scope: oversampling ##################*/
/* Note: Feature not available on this STM32 serie */
/* Note: in this example, ADC group regular end of conversions
(number of ADC conversions defined by DMA buffer size)
are notified by DMA transfer interruptions).
Perform ADC activation procedure to make it ready to convert
(ADC instance: ADC1).
Operations:
- ADC instance
- Enable ADC
- ADC group regular
none: ADC conversion start-stop to be performed
after this function
- ADC group injected
none: ADC conversion start-stop to be performed
after this function
* @retval None
void Activate_ADC(void)
#if (USE_TIMEOUT == 1)
uint32_t Timeout = 0; /* Variable used for timeout management */
#endif /* USE_TIMEOUT */
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Enable ADC */
LL_ADC_Enable(ADC1);
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
/* Note: No operation on ADC group regular performed here.
ADC group regular conversions to be performed after this function
using function:
"LL_ADC_REG_StartConversion();"
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
/* Note: No operation on ADC group injected performed here.
ADC group injected conversions to be performed after this function */
using function:
"LL_ADC_INJ_StartConversion();"
Perform ADC activation procedure to make it ready to convert
(ADC instance: ADC2, used as ADC slave in multimode configuration).
Operations:
- ADC instance
- Enable ADC
- ADC group regular
none: ADC conversion start-stop to be performed
after this function
- ADC group injected
none: ADC conversion start-stop to be performed
after this function
* @retval None
void Activate_ADC_slave(void)
#if (USE_TIMEOUT == 1)
uint32_t Timeout = 0; /* Variable used for timeout management */
#endif /* USE_TIMEOUT */
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Enable ADC */
LL_ADC_Enable(ADC2);
LL_ADC_Enable(ADC3);
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
/* Note: No operation on ADC group regular performed here.
In ADC multimode group regular interleaved, ADC slave conversions
start and stop are controlled by ADC master.
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
/* Note: No operation on ADC group injected performed here.
ADC group injected conversions to be performed after this function */
using function:
"LL_ADC_INJ_StartConversion();"
System Clock Configuration
The system Clock is configured as follow :
System Clock source
= PLL (HSE)
SYSCLK(Hz)
AHB Prescaler
APB1 Prescaler
APB2 Prescaler
HSI Frequency(Hz)
Main regulator output voltage
= Scale1 mode
Flash Latency(WS)
* @retval None
void SystemClock_Config(void)
/* Enable HSE clock */
LL_RCC_HSE_EnableBypass();
LL_RCC_HSE_Enable();
while(LL_RCC_HSE_IsReady() != 1)
/* Set FLASH latency */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_7);
/* Enable PWR clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
/* Activation OverDrive Mode */
LL_PWR_EnableOverDriveMode();
while(LL_PWR_IsActiveFlag_OD() != 1)
/* Activation OverDrive Switching */
LL_PWR_EnableOverDriveSwitching();
while(LL_PWR_IsActiveFlag_ODSW() != 1)
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_8, 432, LL_RCC_PLLP_DIV_2);
LL_RCC_PLL_Enable();
while(LL_RCC_PLL_IsReady() != 1)
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
/* Set APB1 & APB2 prescaler */
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
/* Set systick to 1ms */
SysTick_Config( / 1000);
/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
SystemCoreClock = ;
CPU L1-Cache enable.
* @retval None
static void CPU_CACHE_Enable(void)
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
/******************************************************************************/
USER IRQ HANDLER TREATMENT
/******************************************************************************/
DMA transfer complete callback
This function is executed when the transfer complete interrupt
is generated
* @retval None
void AdcDmaTransferComplete_Callback()
uint32_t tmp_index = 0;
/* For the purpose of this example, dispatch multimode dual conversion data */
/* into arrays corresponding to ADC master and ADC slave conversion data.
/* Note: In a real application, this processing is useless and can be
avoided by setting multimode DMA transfer to one DMA channel
for each of ADC master and ADC slave.
Refer to function "LL_ADC_SetMultiDMATransfer()".
/* Management of the 2nd half of the buffer */
for (tmp_index = (ADC_CONVERTED_DATA_BUFFER_SIZE / 3); tmp_index & ADC_CONVERTED_DATA_BUFFER_SIZE; tmp_index++)
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
aADCyMultimodeDualSlaveConvertedData[tmp_index]
= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
/* Update status variable of DMA transfer */
ubDmaTransferStatus = 1;
USE_FULL_ASSERT
Reports the name of the source file and the source line number
where the assert_param error has occurred.
file: pointer to the source file name
line: assert_param error line source number
* @retval None
void assert_failed(uint8_t *file, uint32_t line)
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d", file, line) */
/* Infinite loop */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**&&******************************************************************************&&* @file&&&&Examples_LL/ADC/ADC_MultimodeDualInterleaved/Src/main.c&&* @author&&MCD Application Team&&* @version V1.0.0&&* @date&&&&30-December-2016&&* @brief&& This example describes how to use several ADC peripherals in&&*&&&&&&&&&&multimode, mode interleaved.&&*&&&&&&&&&&ADC master instance synchronizes and manages ADC slave instance.&&*&&&&&&&&&&Multimode interleaved combines ADC instances to convert&&*&&&&&&&&&&the same channel and increase the overall ADC conversion rate.&&*&&&&&&&&&&This example configures the ADC to perform conversions at the&&*&&&&&&&&&&maximum ADC conversion rate possible (with a sampling time&&*&&&&&&&&&&corresponding to ADC resolution 12 bits).&&*&&&&&&&&&&This example is based on the STM32F7xx ADC LL API;&&*&&&&&&&&&&Peripheral initialization done using LL unitary services functions.&&******************************************************************************&&* @attention&&*&&* &h2&&center&(C) COPYRIGHT(c) 2016 STMicroelectronics&/center&&/h2&&&*&&* Redistribution and use in source and binary forms, with or without modification,&&* are permitted provided that the following conditions are met:&&*&& 1. Redistributions of source code must retain the above copyright notice,&&*&&&&&&this list of conditions and the following disclaimer.&&*&& 2. Redistributions in binary form must reproduce the above copyright notice,&&*&&&&&&this list of conditions and the following disclaimer in the documentation&&*&&&&&&and/or other materials provided with the distribution.&&*&& 3. Neither the name of STMicroelectronics nor the names of its contributors&&*&&&&&&may be used to endorse or promote products derived from this software&&*&&&&&&without specific prior written permission.&&*&&* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"&&* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE&&* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE&&* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE&&* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL&&* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR&&* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER&&* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,&&* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE&&* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.&&*&&******************************************************************************&&*//* Includes ------------------------------------------------------------------*/#include "main.h"/** @addtogroup STM32F7xx_LL_Examples&&* @{&&*//** @addtogroup ADC_MultimodeDualInterleaved&&* @{&&*//* Private typedef -----------------------------------------------------------*//* Private define ------------------------------------------------------------*//* Definitions of ADC hardware constraints delays *//* Note: Only ADC IP HW delays are defined in ADC LL driver driver,&&&&&&&&&& *//*&&&&&& not timeout values:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&&&&& Timeout values for ADC operations are dependent to device clock&&&&&&*//*&&&&&& configuration (system clock versus ADC clock),&&&&&&&&&&&&&&&&&&&&&& *//*&&&&&& and therefore must be defined in user application.&&&&&&&&&&&&&&&&&& *//*&&&&&& Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout&&&& *//*&&&&&& values definition.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//* Timeout values for ADC operations. *//* (enable settling time, disable settling time, ...)&&&&&&&&&&&&&&&&&&&&&& *//* Values defined to be higher than worst cases: low clock frequency,&&&&&& *//* maximum prescalers.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//* Example of profile very low frequency : ADC clock frequency 36MHz&&&&&&&&*//* prescaler 2, sampling time 56 ADC clock cycles, resolution 12 bits.&&&&&&*//*&&- ADC enable time: maximum delay is 3 us&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&&&(refer to device datasheet, parameter "tSTAB")&&&&&&&&&&&&&&&&&&&&&&&&*//*&&- ADC disable time: maximum delay should be a few ADC clock cycles&&&&&&*//*&&- ADC stop conversion time: maximum delay should be a few ADC clock&&&& *//*&&&&cycles&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&- ADC conversion time: with this hypothesis of clock settings, maximum&&*//*&&&&delay will be 99us.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//*&&&&(refer to device reference manual, section "Timing")&&&&&&&&&&&&&&&&&&*//* Unit: ms&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */#define ADC_CALIBRATION_TIMEOUT_MS&&&&&& ((uint32_t)&& 1)#define ADC_ENABLE_TIMEOUT_MS&&&&&&&&&&&&((uint32_t)&& 1)#define ADC_DISABLE_TIMEOUT_MS&&&&&&&&&& ((uint32_t)&& 1)#define ADC_STOP_CONVERSION_TIMEOUT_MS&& ((uint32_t)&& 1)#define ADC_CONVERSION_TIMEOUT_MS&&&&&&&&((uint32_t)&& 2)/* Definitions of environment analog values *//* Value of analog reference voltage (Vref+), connected to analog voltage&& *//* supply Vdda (unit: mV).&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/#define VDDA_APPLI&&&&&&&&&&&&&&&&&&&&&& ((uint32_t)3300)/* Definitions of data related to this example *//* Init variable out of expected ADC conversion data range */#define VAR_CONVERTED_DATA_INIT_VALUE&&&&(__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)/* Definition of ADCx conversions data table size *//* Note: Considering interruption occurring after each number of&&&&&&&&&&&&*//*&&&&&& "ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions&&&&&&&&&&&&&&&&&& *//*&&&&&& (IT from DMA transfer complete),&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//*&&&&&& select sampling time and ADC clock with sufficient&&&&&&&&&&&&&&&& *//*&&&&&& duration to not create an overhead situation in IRQHandler.&&&&&&&&*/#define ADC_CONVERTED_DATA_BUFFER_SIZE&& ((uint32_t) 256)/* Private macro -------------------------------------------------------------*//* Private variables ---------------------------------------------------------*//* Variables for ADC conversion data */__IO&& uint32_t aADCxADCyMultimodeDualConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];&&&& /* ADC multimode dual conversion data: ADC master and ADC slave conversion data are concatenated in a registers of 32 bits. */static uint16_t aADCxMultimodeDualMasterConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];/* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC master conversion data. */static uint16_t aADCyMultimodeDualSlaveConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC slave conversion data. *//* Variable to report status of DMA transfer of ADC group regular conversions *//*&&0: DMA transfer is not completed&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&1: DMA transfer is completed&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&2: DMA transfer has not been started yet (initial state)&&&&&&&&&&&&&&&&&&*/__IO uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback *//* Private function prototypes -----------------------------------------------*/void&&&& SystemClock_Config(void);void&&&& Configure_DMA(void);void&&&& Configure_ADC(void);void&&&& Configure_ADC_slave(void);void&&&& Activate_ADC(void);void&&&& Activate_ADC_slave(void);static void CPU_CACHE_Enable(void);/* Private functions ---------------------------------------------------------*//**&&* @brief&&Main program&&* @param&&None&&* @retval None&&*/int main(void){&&&&/* Enable the CPU Cache */&&&&CPU_CACHE_Enable();&&&&/* Configure the system clock to 216 MHz */&&&&SystemClock_Config();&&&&/* Initialize button in EXTI mode */&&&&/* UserButton_Init(); */&&&&/* Configure DMA for data transfer from ADC */&&&&Configure_DMA();&&&&/* Configure ADC */&&&&/* Note: This function configures the ADC but does not enable it.&&&&&&&&&& */&&&&/*&&&&&& To enable it, use function "Activate_ADC()".&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&& This is intended to optimize power consumption:&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& 1. ADC configuration can be done once at the beginning&&&&&&&&&&&& */&&&&/*&&&&&&&&&&(ADC disabled, minimal power consumption)&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&& 2. ADC enable (higher power consumption) can be done just before&& */&&&&/*&&&&&&&&&&ADC conversions needed.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&&&&&&Then, possible to perform successive "Activate_ADC()",&&&&&&&&&&*/&&&&/*&&&&&&&&&&"Deactivate_ADC()", ..., without having to set again&&&&&&&&&&&&*/&&&&/*&&&&&&&&&&ADC configuration.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&Configure_ADC();&&&&/* For multimode, configure ADC slave */&&&&Configure_ADC_slave();&&&&/* Activate ADC */&&&&/* Perform ADC activation procedure to make it ready to convert. */&&&&Activate_ADC();&&&&Activate_ADC_slave();&&&&LL_ADC_REG_StartConversionSWStart(ADC1);&&&&/* Infinite loop */&&&&while (1)&&&&{&&&&&&&&/* Note: ADC group regular conversion start is done into push button&&&&&&*/&&&&&&&&/*&&&&&& IRQ handler, refer to function "UserButton_Callback()".&&&&&&&&&&*/&&&&&&&&/* Note: LED state depending on DMA transfer status is set into DMA&&&&&& */&&&&&&&&/*&&&&&& IRQ handler, refer to functions "DmaTransferComplete()"&&&&&&&&&&*/&&&&&&&&/*&&&&&& and "DmaTransferHalfComplete()".&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/* Note: ADC conversion data are stored into array&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& "aADCxADCyMultimodeDualConvertedData".&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& For this example purpose, ADC conversion data of ADC master and&&*/&&&&&&&&/*&&&&&& ADC slave are dispatched into arrays */&&&&&&&&/*&&&&&& "aADCxMultimodeDualMasterConvertedData"&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& and "aADCyMultimodeDualSlaveConvertedData", refer to comments&&&&*/&&&&&&&&/*&&&&&& into function "DmaTransferComplete()".&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& (for debug: see variable content into watch window).&&&&&&&&&&&& */&&&&&&&&/* Note: ADC conversion data can be computed to physical values&&&&&&&&&& */&&&&&&&&/*&&&&&& using ADC LL driver helper macro:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&& uhADCxConvertedData_Voltage_mVolt&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&& = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI,&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&uhADCxConvertedData),&&&&&&&&&&&& */&&&&&&&&/*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&LL_ADC_RESOLUTION_12B)&&&&&&&&&&&&*/&&&&}}/**&&* @brief&&This function configures DMA for transfer of data from ADC&&* @param&&None&&* @retval None&&*/void Configure_DMA(void){&&&&/*## Configuration of NVIC #################################################*/&&&&/* Configure NVIC to enable DMA interruptions */&&&&NVIC_SetPriority(DMA2_Stream0_IRQn, 1);&&/* DMA IRQ lower priority than ADC IRQ */&&&&NVIC_EnableIRQ(DMA2_Stream0_IRQn);&&&&/*## Configuration of DMA ##################################################*/&&&&/* Enable the peripheral clock of DMA */&&&&LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);&&&&/* Configure the DMA transfer */&&&&/*&&- DMA transfer in circular mode to match with ADC configuration:&&&&&&&&*/&&&&/*&&&&DMA unlimited requests.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&- DMA transfer from ADC without address increment.&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer to memory with address increment.&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer from ADC by word to match with ADC configuration:&&&&&&&&*/&&&&/*&&&&ADC resolution 12 bits and and multimode enabled,&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&ADC master and ADC slave conversion data are concatenated in&&&&&&&&&&*/&&&&/*&&&&a register of 32 bits.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer to memory by word to match with ADC conversion data&&&&&&*/&&&&/*&&&&buffer variable type: word.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_0, LL_DMA_CHANNEL_0);&&&&LL_DMA_ConfigTransfer(DMA2,&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_DIRECTION_PERIPH_TO_MEMORY |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MODE_CIRCULAR&&&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PERIPH_NOINCREMENT&&&&&&&& |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MEMORY_INCREMENT&&&&&&&&&& |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PDATAALIGN_WORD&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MDATAALIGN_WORD&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PRIORITY_HIGH&&&&&&&&&&&&&& );&&&&/* Set DMA transfer addresses of source and destination */&&&&/* Note: On this STM32 device, in multimode, ADC conversion data with&&&&&& */&&&&/*&&&&&& ADC master and ADC slave conversion data concatenated are located&&*/&&&&/*&&&&&& in a specific multimode data register.&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&LL_DMA_ConfigAddresses(DMA2,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA_MULTI),&&&&&&&&&&&&&&&&&&&&&&&&&& (uint32_t)&aADCxADCyMultimodeDualConvertedData,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_DIRECTION_PERIPH_TO_MEMORY);&&&&/* Set DMA transfer size */&&&&LL_DMA_SetDataLength(DMA2,&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&& ADC_CONVERTED_DATA_BUFFER_SIZE);&&&&/* Enable DMA transfer interruption: transfer complete */&&&&LL_DMA_EnableIT_TC(DMA2,&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0);&&&&/*## Activation of DMA #####################################################*/&&&&/* Enable the DMA transfer */&&&&LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_0);}/**&&* @brief&&Configure ADC (ADC instance: ADC1) and GPIO used by ADC channels.&&* @note&& In case re-use of this function outside of this example:&&*&&&&&&&& This function includes checks of ADC hardware constraints before&&*&&&&&&&& executing some configuration functions.&&*&&&&&&&& - In this example, all these checks are not necessary but are&&*&&&&&&&&&& implemented anyway to show the best practice usages&&*&&&&&&&&&& corresponding to reference manual procedure.&&*&&&&&&&&&& (On some STM32 series, setting of ADC features are not&&*&&&&&&&&&& conditioned to ADC state. However, in order to be compliant with&&*&&&&&&&&&& other STM32 series and to show the best practice usages,&&*&&&&&&&&&& ADC state is checked anyway with same constraints).&&*&&&&&&&&&& Software can be optimized by removing some of these checks,&&*&&&&&&&&&& if they are not relevant considering previous settings and actions&&*&&&&&&&&&& in user application.&&*&&&&&&&& - If ADC is not in the appropriate state to modify some parameters,&&*&&&&&&&&&& the setting of these parameters is bypassed without error&&*&&&&&&&&&& reporting:&&*&&&&&&&&&& it can be the expected behavior in case of recall of this&&*&&&&&&&&&& function to update only a few parameters (which update fullfills&&*&&&&&&&&&& the ADC state).&&*&&&&&&&&&& Otherwise, it is up to the user to set the appropriate error&&*&&&&&&&&&& reporting in user application.&&* @note&& Peripheral configuration is minimal configuration from reset values.&&*&&&&&&&& Thus, some useless LL unitary functions calls below are provided as&&*&&&&&&&& commented examples - setting is default configuration from reset.&&* @param&&None&&* @retval None&&*/void Configure_ADC(void){&&&&/*## Configuration of GPIO used by ADC channels ############################*/&&&&/* Note: On this STM32 device, ADC1 channel 4 is mapped on GPIO pin PA.04 */&&&&/* Enable GPIO Clock */&&&&LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);&&&&/* Configure GPIO in analog mode to be used as ADC input */&&&&LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);&&&&/*## Configuration of ADC ##################################################*/&&&&/*## Configuration of ADC hierarchical scope: common to several ADC ########*/&&&&/* Enable ADC clock (core clock) */&&&&LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);&&&&/* Note: Hardware constraint (refer to description of the functions&&&&&&&& */&&&&/*&&&&&& below):&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& On this STM32 serie, setting of these features are not&&&&&&&&&&&& */&&&&/*&&&&&& conditioned to ADC state.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& However, in order to be compliant with other STM32 series&&&&&&&&&&*/&&&&/*&&&&&& and to show the best practice usages, ADC state is checked.&&&&&&&&*/&&&&/*&&&&&& Software can be optimized by removing some of these checks, if&&&& */&&&&/*&&&&&& they are not relevant considering previous settings and actions&&&&*/&&&&/*&&&&&& in user application.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() == 0)&&&&{&&&&&&&&/* Note: Call of the functions below are commented because they are&&&&&& */&&&&&&&&/*&&&&&& useless in this example:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&