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AR# 34243: Xilinx Memory Interface Solution Center
Xilinx Memory Interface Solution Center
The Memory Interface Generator (MIG) Solution Center is available to address all questions related to the MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the Memory Interface Solution Center to guide you to the right information.
Design Assistant
Xilinx Memory Interface Solution Center - Design Assistant
Select the appropriate Design Assistant below to learn more about designing with a MIG core or to find help on debugging an issue that you are currently encountering. The MIG Design Assistants walk you through the recommend design flow for MIG while debugging commonly encountered issues such as simulation issues, calibration failures, and data errors. The Design Assistants provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with MIG.Note: This answer record is a part of the Xilinx MIG Solution Center . The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
UltraScale MemoryStarting with UltraScale Memory, all design and debug content is organized based on the recommended design flow for MIG within the MIG IP UltraScale Design Checklist.
Please use this checklist through your MIG IP design and debug.7 Series Memory
MIG 7 Series Design AssistantVirtex-6 Memory
MIG Virtex-6 Design AssistantSpartan-6 Memory MIG Spartan-6 Design Assistant
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Documentation
Xilinx MIG Solution Center - Documentation
Please refer to the following documentation when using MIG.
NOTE: This answer record is part of the Xilinx MIG Solution Center .
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
UltraScale Memory Interface Solutions
Please visit the UltraScale MIG Documentation Centre, which includes:
PG150 -
UltraScale FPGAs Memory Interface Performance SpecificationsPlease visit the , which includes:
DS893 -
7 Series Memory Interface Solutions
Please visit the 7 Series MIG documentation center, which includes:
UG586 -
Additional Resources:
7 Series FPGAs Memory Interface Performance SpecificationsPlease visit the , which includes:
Spartan-6 and Virtex-6 Memory Interface Solutions
Please visit the MIG Virtex-6 and Spartan-6 Documentation Centre, which includes:
UG406 -
Additional Resources:Memory Interface Board/Pinout DesignEach MIG User Guide includes sections dedicated to Memory Interface Board/Pinout Guidelines.
Please visit the above noted User Guide specific to your MIG design.
Virtex-5 Memory Interface Solutions
Spartan-3 Generation Memory Interface Solutions
Virtex-4 Memory Interface Solutions
Revision History
01/27/2014
Minor updates
11/15/2011
Updated to point to MIG documentation pages
04/06/2011
Added WP383 and XAPP868
03/01/2011
Added 7 Series Memory Interface Documentation
Design Advisories
Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
For a list of all current Release Notes and Known Issues for Xilinx Solutions for MIG, please refer to the IP Release Notes Guide (XTP025):
For general design and troubleshooting information on MIG, please refer to the Xilinx MIG Solution Center at:
UltraScale MIG12/20/2016Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs 07/06/2015Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization10/27/2014Design Advisory for MIG UltraScale (all memory types) - VRP pin required for all I/O banks including output only banks 10/13/2014Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Planner 7 Series DDR3 MIG
03/23/2016Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures 11/23/2015Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin 10/12/2015Updated Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces11/19/2014Design Advisory for MIG 7 Series DDR3 - Calibration updates in MIG 7 Series v2.3 available with Vivado 2014.4 provide additional write margin 06/11/2014Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to &FAST& for synthesis and implementation 06/02/2014Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces11/11/2013Design Advisory for MIG 7 Series DDR3/DDR2 - MIG includes incorrect maximum frequencies for 2:1 (half-rate) DDR3/DDR2 controller designs targeting -2 and -1 speed grades. Maximum spec numbers in datasheets are correct.04/22/2013Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied. RTL Updates Required.04/22/2013Design Advisory for MIG 7 Series LPDDR2 - MIG allows incorrect placement of CK/CK# pairs when using the &Verify Pin Changes and Update Design& and &Fixed Pin-Out& flows. Documentation and &New Design& flow are correct.01/28/2013Design Advisory for MIG 7 Series DDR3 - All CK clock pins must to be in the same byte lane/group. Validating Dual Rank Pin-Outs Required.01/28/2013Design Advisory for MIG 7 Series v1.8 RLDRAM II - Pinout violation not detected in &Fixed Pin Out& mode or &Verify Pin Changes and Update Design& flow.01/21/2013Design Advisory for MIG 7 Series QDRII+ - Inferred latches cause write calibration failures. Work-around required.01/07/2013Design Advisory for MIG 7 Series DDR3/DDR2 - Required calibration patch for v1.7 and v1.812/10/2012Design Advisory MIG 7 Series QDRII+ - Read calibration failures can occur when CPT_CLK_CQ_ONLY=FALSE10/24/2012Design Advisory MIG 7 Series DDR3 - Issue with OCLKDELAY calibration causes write DQS to be aligned to DQ with potential calibration failures10/24/2012Design Advisory MIG 7 Series DDR3/DDR2 - Temperature monitor calibration using XADC block added to all DDR3/DDR2 designs in v1.7 (ISE 14.3/Vivado 2012.3) 08/20/2012Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases 08/06/2012Design Advisory MIG 7 Series v1.6 - Calibration updates for all interfaces05/14/2012Design Advisory MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1) 03/12/2012Design Advisory MIG 7 Series v1.4 DDR2/DDR3 - Calibration Update. Revised patch from 2/23/2012. Required for designs targeting Initial Engineering Sample devices.02/23/2012Design Advisory MIG 7 Series v1.4 DDR2/DDR3 - Calibration Update01/10/2012Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified05/05/20117 Series MIG DDR3 - Internal/External Vref Guidelines 05/02/2011MIG 7 Series 1.1 DDR3 SDRAM - Addr/Cntrl pins should be limited to a single bank04/11/2011MIG 7 Series 1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications Spartan-6 FPGA MCB04/25/2011MIG v3.7 Spartan-6 MCB - Certain User Port Configurations do not work for VHDL designs04/18/2011Spartan-6 MCB Design Advisory - Removal of VCCINT restrictions to reach maximum DDR3 data rates11/09/2010MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration.06/14/2010MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs. 06/14/2010MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required. 06/14/2010Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces.02/08/2010MIG v3.3, Spartan-6 FPGA MCB - Incorrect port connection causes Continuous DQS Tuning to behave incorrectly - Manual modification required.02/08/2010MIG v3.3, Spartan-6 FPGA LPDDR - Calibrated and Un-Calibrated Input Termination features not supported.02/08/2010MIG v3.3, Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?02/08/2010MIG v3.3, Spartan-6 FPGA LPDDR - Drive strength selected in MIG is not properly set in the output design.02/08/2010MIG v3.3, Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device.09/23/2009Spartan-6 FPGA MCB - Data Mask cannot be disabled and the UDM and LDM pins cannot be used as General Purpose I/O (GPIO). Virtex-6 DDR2/DDR3 MIG 03/9/2010MIG v3.0-3.3, Virtex-6 FPGA DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue. 02/8/2010MIG 3.3, Virtex-6 FPGA DDR3 - Write Leveling does not succeed and calibration fails due to IDELAYCTRL not being automatically inferred by the software.02/8/2010MIG v3.3, Virtex-6 FPGA DDR2/DDR3- MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required
To update your Xilinx Alert Notification Preferences, please go to:
Revision History03/08/2017Added 6, 610/12/2015Added update to 5916707/06/2015Added 6485610/22/2014Added 62483 and 62157 06/04/2014Added 5916711/11/2013Added 5817204/18/2013Added 55531 and 5553601/28/2013Added 53919 and 5386001/21/2013Added 5360701/07/2013Added 5342012/10/2012Added 5305310/24/2012Added 51687 and 5257308/20/2012Added 5129608/06/2012Added 5046105/14/2012Added 4704303/12/2012Added updated patch for 4565302/23/2012Added 4565301/10/2012Added 4563305/05/2011Updated 7 Series DDR3 MIG to include 4203605/02/2011Updated 7 Series DDR3 MIG to include 4198104/18/2011Updated Spartan-6 list to include 4152004/11/2011Added 7 Series and included 40876 and 41351 (Since obsoleted)11/09/2010Updated Spartan-6 list to include 3629106/14/2010Updated Spartan-6 list to include 3, and 3581803/09/2010Updated list to include 3420402/08/2009Updated list to include 3, 3, 3, and 3409409/28/2009Initial R added 33358
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Top Issues
Xilinx MIG Solution Center - Top Issues and Frequently Asked Questions (FAQ)
The following answer records cover current known issues as well as commonly asked questions related to MIG.
NOTE: This answer record is part of the Xilinx MIG Solution Center .
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Please select the appropriate MIG product below:
MIG UltraScale Solution Center - Frequently Asked Questions (FAQ) MIG 7 Series Top Issues MIG Virtex-6 and Spartan-6 Top Issues
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Share This PageHas anyone implemented the I2C controller core mentioned in the xapp333
in a FPGA.
I have simulated the core to set the address register. and it works in
simulation. when i try to that there are problems during synthesis. i
think its got something to do with dual INPUTOUTPUT ports.
The synthesis tool keeps saying there are multisources and because of
which i think something has gone wrong with the DTACK signal and there
are problems.
I have pasted the part from synthesis report because of which i think
the problems arise.
meanwhile if anyone else has implemented the I2C controller core and
could give me tips it would be really helpful.
Thanks in advance
WARNING:Xst:2040 - Unit i2c_tb: 8 multi-source signals are replaced by
logic (pull-up yes): data_bus&0&, data_bus&1&, data_bus&2&,
data_bus&3&, data_bus&4&, data_bus&5&, data_bus&6&, data_bus&7&.
WARNING:Xst:2042 - Unit uC_interface: 9 internal tristates are replaced
by logic (pull-up yes): data_bus&0&, data_bus&1&, data_bus&2&,
data_bus&3&, data_bus&4&, data_bus&5&, data_bus&6&, data_bus&7&, irq.
WARNING:Xst:2183 - Unit i2c_control: the following tristate(s) are NOT
replaced by logic (Please refer to Answer Record 20048 for more
information): scl, sda.
WARNING:Xst:1906 - Unit uC_interface is merged (output ports from
interface drive multi-sources)
18587 articles.
2 followers.
11 Replies
1530 Views
[PageSpeed]
I have implemented a I2C bus core by myself.
When reading, a multiple source 'error' would happen if your code
assertes the acknowledge bit slightly earlier than the target deasserts
the bus from the last read data bit or when writing, if your code
deasserts the acknowledge bit slightly later than the target asserts
the acknowledge bit on the bus.
You may ignore them totally without any problem.
&& schrieb im Newsbeitrag
news:.220@f14g2000cwb.googlegroups.com...
& I have implemented a I2C bus core by myself.
& When reading, a multiple source 'error' would happen if your code
& assertes the acknowledge bit slightly earlier than the target deasserts
& the bus from the last read data bit or when writing, if your code
& deasserts the acknowledge bit slightly later than the target asserts
& the acknowledge bit on the bus.
& You may ignore them totally without any problem.
http://xilant.com/content/view/31/55/
Weng, the multipy source error is usually fatal synthesis error and prevents
the bitstream generation until fixed.
the OP has problem wiring up the processor data bus, not the SDA/SCL lines
Thank you for indicating my wrong answer.
I misunderstood the problem.
One of errors is multi-source data_bus(7 downto 0) are assigned in more
than one processes!
It is easy to correct it:
Use search key to search signal 'data_bus' through the module source
file and see how many times the data_bus are assigned. Put all
assignments in one process only.
&& schrieb im Newsbeitrag
news:.40@g14g2000cwa.googlegroups.com...
& Hi Antti,
& Thank you for indicating my wrong answer.
& I misunderstood the problem.
& One of errors is multi-source data_bus(7 downto 0) are assigned in more
& than one processes!
& It is easy to correct it:
& Use search key to search signal 'data_bus' through the module source
& file and see how many times the data_bus are assigned. Put all
& assignments in one process only.
Weng you are a bit mistaken again the data_bus is assigned once outside
data_bus &= data_out when (r_w = '1' and dtack_oe = '1') else (others =&
'Z');
in the uc_interface.vhd
so the ip-core is 100% proper for its intended function - controller for
external microcontroller.
for on-chip soc bus, the uc_interface module should be replaced, or
I don't have his source code and made a judgement based on the
following warnings:
Unit i2c_tb: 8 multi-source signals are replaced by
logic (pull-up yes): data_bus&0&, data_bus&1&, data_bus&2&,
data_bus&3&, data_bus&4&, data_bus&5&, data_bus&6&, data_bus&7&.
1. data_bus are multi-
2. data_bus is in the module: i2c_tb. It may be in his test bench code
to make the multi-source error.
I never claimed that it was the IP code error. Any IP code never makes
such basic and fundamental error.
&& schrieb im Newsbeitrag
news:.280@g44g2000cwa.googlegroups.com...
& Hi Antti,
& I don't have his source code and made a judgement based on the
& following warnings:
& Unit i2c_tb: 8 multi-source signals are replaced by
& logic (pull-up yes): data_bus&0&, data_bus&1&, data_bus&2&,
& data_bus&3&, data_bus&4&, data_bus&5&, data_bus&6&, data_bus&7&.
& 1. data_bus are multi-
& 2. data_bus is in the module: i2c_tb. It may be in his test bench code
& to make the multi-source error.
& I never claimed that it was the IP code error. Any IP code never makes
& such basic and fundamental error.
no problems - I just checked the original - form without doing that your
guess was 'close'
Thanks for your discussion.
I figured so much that we cannot be using the bidirectional buses all
over the program.
but i for sure have my doubts on whether the IP core is 100%proper even
just as an individual unit.
The reason is after the address match where the I2C controller is
addressed as slave it does not send the acknowledge bit. I have enabled
both the options in the control register and checked it but to no
Antti Lukats wrote:
& && schrieb im Newsbeitrag
& news:.40@g14g2000cwa.googlegroups.com...
& & Hi Antti,
& & Thank you for indicating my wrong answer.
& & I misunderstood the problem.
& & One of errors is multi-source data_bus(7 downto 0) are assigned in more
& & than one processes!
& & It is easy to correct it:
& & Use search key to search signal 'data_bus' through the module source
& & file and see how many times the data_bus are assigned. Put all
& & assignments in one process only.
& Weng you are a bit mistaken again the data_bus is assigned once outside
& data_bus &= data_out when (r_w = '1' and dtack_oe = '1') else (others =&
& 'Z');
& in the uc_interface.vhd
& so the ip-core is 100% proper for its intended function - controller for
& external microcontroller.
& for on-chip soc bus, the uc_interface module should be replaced, or
& modified.
1. I2C IP is so simple that it will never fail, in my opinion.
2. You are a newbie in this respect, the chance you make a mistake is
beyond 99%.
3. If I2C controller contained in the IP doesn't send the acknowledge
bit, your design is fundamentally wrong.
Can you imagine an IP fails to response with an acknowledge bit?
You may post your code and I will help you ID the first error, not all
&& schrieb im Newsbeitrag
news:.30@g14g2000cwa.googlegroups.com...
& 1. I2C IP is so simple that it will never fail, in my opinion.
simple things fail too, and too often
& 2. You are a newbie in this respect, the chance you make a mistake is
& beyond 99%.
NO, the chances for an total newbie to get things right are defently better
& 3. If I2C controller contained in the IP doesn't send the acknowledge
& bit, your design is fundamentally wrong.
& Can you imagine an IP fails to response with an acknowledge bit?
& You may post your code and I will help you ID the first error, not all
The I2C core at opencores had been available for many years, still when I
needed it I found a fundamental error in it. So similary the XAPP333 may
have error in it as well
Antti Lukats
http://www.xilant.com
& 1. I2C IP is so simple that it will never fail, in my opinion.
There are a well know errors with I2C, one way with half finished
transmissions where on partner in the transmission keeps pulling SDA or SCL
low. SMBus introduces timeouts into the protocoll, pure I2C may need to
switch off the partner, pulling the bus low. Sometimes this has to be done
with the supply line...
Uwe Bonnes
bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik
Schlossgartenstrasse 9
64289 Darmstadt
--------- Tel.
-------- Fax.
----------
I am surprised to learn your opinions:
1. &simple things fail too, and too often&, I agree.
2. &NO, the chances for an total newbie to get things right are
defently better than 1%&, I disagree.
Let's see what is wrong with his problem.
Similar Artilces:
I'm searching for a FPGA board for about $500 with an &audio in& and &audio
out& port... adequate for audio processing applications. I thought of a
Virtex II fpga, but can be another one from XILINX....
Can anyone recommend a board like this ?
Timo Dammes
&Timo Dammes& &timo.dammes@gmx.de& wrote in
news:cdghf4$1gq$1@nx6.HRZ.Uni-Dortmund.DE:
& I'm searching for a FPGA board for about $500 with an &audio in& and
& &audio out& port... adequate for audio processing applications. I
& thought of a Virtex II fpga, but can be another one from XILINX....
& Can anyone recommend a board like this ?
We offer the XST-2 Board that has an AK4551 stereo audio codec:
http://www.xess.com/prod033.php3
You combine it with one of our XSA-50 or XSA-100 Boards:
http://www.xess.com/prod026.php3
Or look at the XSB-300E Board with an AK4565 stereo audio codec:
http://www.xess.com/prod032.php3
& Regards,
& Timo Dammes
----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
http://www.xess.com
Not quite off the shelf but our Broaddown2 will accept 3.3V DIL packaged codecs etc or stripboard based interfaces. &br&&br&Broaddown2 is Spartan-3 based. Broaddown2 details are here &a href=&http://www.enterpoint.co.u...Hi,
I'm actually working on a Xilinx program in VHDL. I'd wish to begin again a part of this program, and it will be easier for me to create it with Labview FPGA.
My idea is to create a sub program in my existing VHDL program, and make this sub program thanks to Labview FPGA.
I know we can't get the VHDL code create by Labview to download it on another FPGA (because Labview FPGA is only for use on Xilinx). But I'd wish to download my program on a Xilinx Virtex 2 Pro.
So, is there a solution to integrate my Labview FPGA program as a sub program in my VHDL code (for a ...
I would like to connect 3 FPGA devices together using a 32-bit bus. Also
would like all 3 to be masters on the bus. Is there any standard bus ou
there that would do this rather than me coming up with my own idea.
On Oct 16, 2:48 pm, &maxascent& &maxasc...@yahoo.co.uk& wrote:
& I would like to connect 3 FPGA devices together using a 32-bit bus. Also I
& would like all 3 to be masters on the bus. Is there any standard bus out
& there that would do this rather than me coming up with my own idea.
Search for hypertunnel (HT) chip-to-...Hi
Any body used FFT core given by coregenerator in Xilinx ?
Does it work as they said in their data sheet..
regards bijoy
bijoy wrote:
& Any body used FFT core given by coregenerator in Xilinx ?
& Does it work as they said in their data sheet..
& regards bijoy
It works very well, it is efficient, and has lots of nice features.
As for any macro, I would recommend making some (RTL) simulations
to ascertain how it must be initialized and used.
Bert Cuzeau
&info_& &&info_&@\\nospam_no_underscore_alse-fr.com& wrote in message
...Hello All.....
I have a few questions concerning FPGA controls, update rates, etc.....
1) In my FPGA application, I have a single-cycle timed loop (SCTL) running at 25ns/tick (it is set up as a state machine).& I update an FPGA FP Boolean with TRUE on each tick as it is running.& When running the FPGA VI FP, does this generate any more &update& traffic to the host?& Or are all front panel controls continuously refreshed at an asynchronous rate.& That is, does the actual assignment of the value to the control cause the update, ...Hi,
I& have a FPGA : Processor Xilinx XC2S30
and&platform : Digilent, Digilab 2XL
Is labview compatible in some ways&?
If yes how ? and,
What Labview can do better than Xilinx (simulink, Matlab)?
If no, what Platform I can use ?
CompactRio seems to be heavy ?
What avantages I can have with this configuration ?
Hi,you might be interested in this:Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUPhttp://zone.ni.com/devzone/cda/tut/p/id/6930RegardsStephan A.NI
...Hi All,
I am new to FPGAs and my main interest is implementation of some
signal processing algorithms on FPGAs. For testing the MEMEC
V2MB1000) board which has a xc2vc1000 fpga on it along with a xc18v04,
I was trying to write a simple module. I am using the impact Parallel
IV cable for download of my code.
I started with a simple VHDL code for a counter to be displayed on 7-
segment display. Since it did not work, I slowly started removing code
and now I have a single
line in the architecture
architecture board of testLed
led &= '1';
The &led...Hi all,
I am needed to talk with a microcontroller through an I2C interface
from my FPGA. I dont want to write a code for it as well not use
opensource core. This is partly due to space constraints and testing.
Speed and cost are not constraints.
So I was hoping to find a chip which would sandwich between the FPGA
and I2C interface.
Searched on the net but could not find any. If anyone has suggestions
please let me know.
vasudev srinivasan
&& schrieb im Newsbeitrag
news:.480@z14g2000cwz.googlegroups.com...
...Regards:
What is the diffrences between lattice's FPGA and Xilinx's FPGA
Thank You.
Best Regards to you all.
On 20 Aug :04 -0700,
& What is the diffrences between lattice's FPGA and Xilinx's FPGA
Lattice FPGAs are made by Lattice at http://www.latticesemi.com/
Xilinx FPGAs are made by Xilinx at http://www.xilinx.com/
There are 7 letters in Lattice
There are 6 letters in Xilinx
If you want better answers, you need to ask better questions.
Let me help you:
Tell us what research you have already ...Hi!
I am currently working on scheduling / partitioning algorithms for
Multi-Level Task handling using Xilinx Vertex II Pro. Do anybody know
if some work have been done on partitioning algorithms for assignment
of tasks to Embedded Microprocessor (embedded in FPGA - Xilinx Vertex
II Pro) and FPGA it self.
Farhan A Chughtai
Undergrad.
University of Engineering and Technology,Lahore
...Currently, when trying to download the bitstream to this SP605 board,
I get the following error:
FPGA configuration encountered errors.
Program FPGA failed
ERROR: Connection to Board Failed
Failed to Open JTAG Cable
Check the following:
1. Cable is Connected to the Board and the Board is Powered-ON
2. On Cable Lock Error, Close the other application using the
cable or Remove Cable Locks using &xclean_cablelock& command
3. You have specified the correct JTAG settings for cable type and
So basically the SDK is not seeing the board. It's odd,...Hello all,
We have made a PCI board using Xilinx PCI core. with master and target capabilities. It works well with intel PCs, but with AMD PCs if i plug the card the PC will not boot.
Does any one had similar expereince ? Any pointers for the cause will be helpful for me
Thank you bijoy
i have a problem to realize the PCI interface.....
can you help me????
how can i do??
i have ML455 board VIRTEX4 PCI
how can i do to comunicate with bus PCI??
i have bought the CORE but i
don't know how can i use it and how create a driver..
please help me.
&bijoy&quot...hi,
i'm writing a linux device driver for the celoxica rc1000 board.
Seems that i can't write to any of the fpga control registers on BAR3
(of PCI9080 config space). Reading access seems to be alright because
the returned values match those mentioned in the hardware reference
manual (in state after power-up).
Reading AND writing to the plx-control-registers (BAR0) and to FPGA
RAM (BAR2) is also no problem.
Any suggestions?
My goal was to transfer an Assembler implementation that was running
on an ARM chip
to the PowerPC 405 architecture on a Xilinx Virtex II Pro. In the
meantime this is working but for some reason the PowerPC
implementation is more than 10 times!!! slower than the ARM chip
implementation. I can only think of
3 reasons:
1) In the ARM implementation I save 16 registers on the stack, whereas
I save 32 registers when working with the
// save register and set up the stack frame
1, 1, -124
// do some stuff
3, 8(1) ...Hi all
I ned an FPGA bord to practice FPGA with VHDL .
That board will hopefully serve me in my first &real& payed FPGA
design projects.
Can you offer me a not so expensive board please ?
Thanks in advance
On Feb 2, 7:55=A0am, TheRightInfo &therighti...@gmail.com& wrote:
& I ned an FPGA bord to practice FPGA with VHDL .
& That board will hopefully serve me in my first &real& payed FPGA
& design projects.
& Can you offer me a not so expensive board please ?
& Thanks in advance
Its not that simple. di...Hi,
I'm a new user of fpga, actually i'm learning about it and i need
I want to know how import cpu's cores (8051 or z80) into a xilinx fpga
device ( Spartan IIe ). If someone can send me a tutorial where i can
learn about that i thanks a lot.
Try http://www.fpgacpu.org/
Arturo Rios wrote:
I'm a new user of fpga, actually i'm learning about it and i need
& I want to know how import cpu's cores (8051 or z80) into a xilinx fpga
& device ( Spartan IIe ). If someone can send me a tutorial where i can
& learn about th...Do anyone know the procedure of installing the system generator. please
...I googled for s g.723.1 codec ipcore for xilinx FPGA but didn't find
Please help!
On Mar 13, 9:59=A0pm, GaLaKtIkUs=99 &taileb.me...@gmail.com& wrote:
& I googled for s g.723.1 codec ipcore for xilinx FPGA but didn't find
& Please help!
I Googled for &Next Week's Winning Lotto Numbers& and didn't find
those either.
Here's a couple of links for you:
&http://www.vhdl-online.de/tutorial/englisch/inhalt.htm&
&http://en.wikipedia.org/wiki/G.723.1&
On Mar 15, 8:39=A0pm, d_s_klein &d_s_kl...@yah...I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA& are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your ...WHAT IS VHDL?
zqTOtyDOo86szrLOss6xz4TOvywgNiDOo861z4DPhM61zrzOss+Bzq/Ov8+FIDIwMTQgMTA6MTk6
MDggzrwuzrwuIFVUQyszLCDOvyDPh8+Bzq7Pg8+EzrfPgiBhYW1pcnMuLi5AZ21haWwuY29tIM6t
zrPPgc6xz4jOtToNCj4gV0hBVCBJUyBWSERMPw0KDQpGb3IgbG92ZSBvZiB0aGUgZ2FtZToNCg0K
aHR0cDovL2VuLndpa2lwZWRpYS5vcmcvd2lraS9WSERMDQoNClNoYW1lbGVzcyBwbHVnOiANCmh0
dHA6Ly93d3cubmthdnZhZGlhcy5jb20vdmhkbC1jb3Vyc2UuaHRtbA0KDQpCZXN0IHJlZ2FyZHMN
Ck5pa29sYW9zIEthdnZhZGlhcw0KaHR0cDovL3d3dy5ua2F2dmFkaWFzLmNvbQ0K
...I would like to generate a current waveform with a signal generator.
Is it possible to build a current generator with a FPGA? I mean a device which accepts a input voltage and give an output current?
If the answer is yes, which is the dynamic?
Thanks a lot
...hello everyone......
anyone can tell me how to convert matlab simulation model to HDL code. or how to generate HDL code from simulink model.
Thanks in Advance
&Lalit Kumar& && wrote in message &ijo9g5$g8h$1@fred.mathworks.com&...
& hello everyone......
& anyone can tell me how to convert matlab simulation model to HDL code. or how to generate HDL code from simulink model.
& Thanks in Advance
http://www.mathworks.com/fpga-design/simulink-with-mentor-graphics-fpga-solutions.html ?
http://www.mathworks.com/products/s...Free Manpower Recruitment Service for recent graduate FPGA Engineers
http://www.fpgasps.com/
...Can i programme non-xilinx fpga through xilinx impact tool & by using
xilinx parrellel four cable?
On Apr 26, 11:41 pm, mohan &kulka...@math.net& wrote:
& Can i programme non-xilinx fpga through xilinx impact tool & by using
& xilinx parrellel four cable?
Using their cable?
Sure, you just need software to drive it.
might have to operate it in a slower bit bang sort of mode.
Using impact?
maybe, but it won't be easy.
If you can get the data
and algorithm into a generic form that impact will execute, such as
maybe an SVF, you might be able to do it that w...
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