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cbulogin.center.eu13Server is OK电赛必备，IR2104S半桥驱动MOS管电机驱动板（PCB工程文件+磁悬浮代码）
MOS管板设计心得：（1）驱动电路方案为经典的半桥驱动IR2104S加N沟道MOS管，MOSEFT内部有续流二极管，听说是寄生的（不知对不对），所以外加了肖特基二极管1N5819；（2）半桥驱动IR2104S自己可以通过自举升压来获得足够的栅压，但是觉得自举电容参数不好精准的确定，而且敏感，故另外外加升压电路，升压电路也为MC34063的经典电路，成熟稳定，用着放心。只是注意电感的选择，应该选择功率电感。（3）隔离也是很重要的，本来想采用光耦隔离，但是想到这是一个单电源系统，光耦隔离未必效果最佳，最重要的一点是，光耦必须选择高速光耦，上网一查，他们的封装都巨大，为了板子的美观（有可能也是节省板子面积少点打板费，这几天饭都吃不， 哎！）。最后选择的是74LVC245，以前都是用244的，第一次用这个，当然也是因为他的封装面积小。（4）正反转指示灯必须的加嘛。我把磁悬浮的视频也给大家分享下吧，姑且当做是对本驱动板的测试视频吧，这个主控板是XS128，调好后会很稳定的。见“相关文件”下载磁悬浮代码。代码写得不是很好，很简单，仅供参考。这个是视频：IR2104S半桥驱动MOS管电机驱动板实物展示：IR2104S半桥驱动MOS管电机驱动板电路 PCB截图：
电路相关文件(请在PC端查看下载)
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使用说明：直接使用附件资料或需要对资料PCB板进行打样的买家，请先核对资料的完整性，如果出现问题，电路城不承担任何经济损失！
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该直流电机驱动板可以同时驱动四路直流电机或者两路二相四线步进电机，通过连接标注的I2C接口到主控，可以对各个电机接口进行配置和驱动。该电机驱动板采用STM8S105作为电机驱动微处理器，负责解析由上位机发送的指令，通过计算后转换成电机驱动信号，支持最高刷新频率（数据更新频率）1ms/次。采用了两颗TB6612FNG高性能电机驱动芯片，静态下，功耗仅30mA，电机驱动能力高达1.2A@5V，峰值电流高达3.2A@5V，电机驱动支持4~12V宽电压（电机驱动供电）输入。其次，该TB6612FNG直流电机驱动板还提供了4路独立舵机驱动接口，可以直接通过主控来驱动舵机。实物截图：技术规格： 驱动主控：STM8S105控制电路工作电压：3.3-5V (连接到FireBeetle的VCC)控制电路工作电流：30mA电机驱动芯片：TB6612FNG电机驱动电压：4-12V电机驱动能力：1.2A平均电流@5V峰值电流：3.2A@5V通信接口：I2C接口设备地址：0x18最大刷新频率：1ms工作模式：4路直流电机或2路步进电机支持4路舵机驱动一个状态指示灯外形尺寸: 58mm x 29mm安装孔尺寸：3.1mm x 6mm安装孔位置: 53mm x 24mm安装孔尺寸：内径3.1mm/外径6mmLED状态指示灯说明 状态1：LED灯闪烁（频率30Hz），说明电机驱动芯片正在等待主机发送初始化指令。状态2：LED常亮，说明电机驱动芯片正常工作（控制电机运转并且等待主机发送新的指令）。状态3：LED熄灭，说明电机驱动芯片出现通讯异常。示例代码截图：
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该L298P直流电机驱动板是Arduino作品中最入门、使用最广泛的电机驱动，常备一款在手边，会让你的制作事半功倍。这款基于L298芯片的Arduino平台双路电机驱动扩展板，可以直接插入Arudino控制板使用。控制端口为4个，减少了对Arduino数字端口的开销，而且控制程序也更为简单。该L298P电机驱动Arduino扩展板扩展板可用跳线选择Arduino VIN供电还是外接电源供电。最大电压可达35V。L298P直流电机驱动板连线图：技术规格：
驱动工作电压：4.8 ～ 35V最大输出电流：单路2A最大耗散功率：25W（T=75℃）驱动形式：双路H桥驱动驱动电源接口：一路外部电源端子 / Arduino-VIN驱动输出接口：两路电机接线端子 / 排针Arduino控制端口：数字口10,11,12,13工作温度：-25℃ ～ 130℃模块尺寸：56x57mm注意：由于L298P直流电机驱动板Arduino应用完整使用教程篇幅过长，所以建议查看原文链接。L298P直流电机驱动板在小车的典型应用：
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四轴步进电机控制器特性介绍：1.单颗MCU（dsPIC33）实现四轴联动控制2. 支持S型，T型曲线加减速，最大输出脉冲可达1MHz（为保证曲线平滑，实际使用为1.4Hz-100KHz）。3. 支持CAN总线级联（最大256块控制器级联）支持超过1000轴并行控制。4. 支持内部flash存储运动参数：加\减速度，最大速度、启动时间等5. 支持IO触发，扩展光耦触发启动或停止，外扩电磁阀等开关量输出附件提供PCB图纸，BOM，设计文档全面资料。软件资料需额外购买，地址：http://www.cirmall.com/circuit/9304/附件资料截图：
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本作品是通过TI官方的FDC2214（两个电容传感器）评估模块 重新修改设计而来，方便使用调试程序。FDC2214EVM（评估模块）演示了如何使用电容感应技术来检测任何导电或非导电目标对象的存在。此模块包括与 FDC2214 的四个通道中的两个相连接的两个示例 PCB 电容传感器。用户可通过第一个穿孔取下模块上的电容传感器，并使用定制的传感器设计进行实验。用户可通过第二个穿孔将 FDC2214 和电容传感器连接到另一个微控制器系统。2018年TI杯省级电子设计竞赛赛题指定使用芯片
为了更好地将业界最新的芯片和技术与竞赛相结合，促进产学合作。在TI杯竞赛中，TI会针对部分赛题指定专用芯片。为了让参赛学生能够更好地培训和在竞赛过程中呈现作品，我们现公布2018年TI杯省级大学生电子设计竞赛指定和建议使用的芯片，为同学们争取更充分的技术学习和芯片准备时间。
在2018年的竞赛中，需要同学们注意提前准备如下器件：1、指定使用器件FDC2214
FDC2214基本介绍 FDC2214是TI最新的一款低功耗、低成本高分辨率的非接触式电容式传感器。该芯片是基于LC谐振电路原理的一款电容式检测传感器。其基本原理如下图所示。2DPCB图片：3D 实物预览：
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固态继电器在电力电子功率器件中又称为无触点开关。基于隔离器件实现控制端与负载端的隔离。虽然固态继电器的输入端用微小的控制信号，但是能够达到直接驱动大电流负载。此固态继电器典型应用电路设计主要用于控制电机驱动中的正转、反转。说明：附件内容提供的原理图来源于某品牌固态继电器内部图
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1、整个电机驱动两轮机器人系统有12V锂电池输入，经过LM2596-5V稳压到5.V给WS2812，TB6612等芯片供电，大电流输出且假如自恢复保险丝；5V经过LDO-LM1117稳压为3.3V给主控供电；2、通过MPU6050输出信号，快速控制机身姿态；3、增加CP2012做为系统串口调试接口；4、通过时序控制WS2812闪烁，作为系统工作指示；5、整个系统中，特别是驱动电机部分将数字地与模拟地进行了隔离，防止耦合干扰；PCB尺寸：110MMX75MM （其中元件3D为1：1结构干涉），整个板子已经小批量试产完成。TB6612+MPU6050电机驱动两轮机器人电路 PCB 截图：
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该3D打印机步进电机驱动板基于LV8729设计，5路驱动，最高支持128细分，采用进口拨码开关设置细分，用料十足，加上散热器完美散热。板子标注清晰明了，一看就知道怎么用。3D打印机LV8729步进电机驱动板电路 PCB截图：3D打印机LV8729步进电机驱动板实物截图：
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采用德州仪器入门款FOC控制芯片TMS320F28027F，参照官方BOOSTXL-DRV8301开发套件设计，取消SPI通讯，释放IO口用于PWM捕获以及串口通讯等(官方DEMO也只用到默认配置，根本用不着SPI修改配置)。可支持到52V的电源输入，自带1.5ABUCK，带各种保护。建议先用MOTORWARE的LAB2b检测电机参数和偏置电压，再修改user.h，编译运行lab10，即可实现一款电机的完美驱动。仿真器建议选择隔离版仿真器，否则电机一转debug就丢失target仿真器EMU1 EMU2需要外部拉高目前性能与官方开发板一致，加减速换向流畅迅速，堵转电流等于启动电流，不大于0.5A，不怕电机烧毁声音极轻，带TMOTOR-U8电机效率相比于好盈铂金提升10%以上，除了桨叶声几乎没有其他杂音原理图确保准确无误，PCB可以按照需求修改基于TMS320F28027F/DRV8301的FOC电调实物截图：
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距离2015年全国电子设计大赛过去2年之后，近期笔者优化电路设计和代码，提高系统稳定性，减小纹波噪声。之所以依旧优化STC方案的数控电源，是方便学生快速学习数控电源，以便入门。但不得不说，单纯的STC数控电源，精度低，纹波大，响应时间久，系统不稳定。但是数控电源的思路都是一样的，拓扑+反馈。总之是学生参加电赛的必备资料，可联系芯兴工作室。
U2=30V 条件下，实现对电池恒流充电。 充电电流 I1 在 50mA~4000mA 范围内步进可调，步进值为50mA， 电流控制精度不低于 5%。设定 I1=2A， 调整直流稳压电源输出电压，使 U2 在 24~36V 范围内变化时，要求 充电电流 I1 的变化率不大于 1%。 （实测 0.5%）设定 I1=2A，在 U2=30V 条件下， 变换器的效率?1 ? 90% 。
（实测 91%）测量并显示充电电流 I1， 在 I1=50mA~4000mA 范围内测量精度不低于 2%。
（实测 1%）具有过充保护功能：设定 I1=4000mA， 当 U1 超过阈值 U1th=24±0.5V 时， 停止充电。
(实测 23.8V)发挥部分：
断开 S1、接通 S2， 将装置设定为放电模式，保持 U2=30±0.5V， 此时变换器效率 95% 。
（实测小于 92%）在满足要求的前提下简化结构、减轻重量，使双向 DC-DC 变换器、测控电路与辅 助电源三部分的总重量不大于 500g。其他。（自己可以添加设计短接，反接保护。本作品具有显示输入输出电压，以及软件上的软启动）。具体单纯的buck boost输入指标：
输入电压：15-35V；输出电压：1-40V；输出电流50mA- 4000mA；最大功率不超过150W；不可为精密仪器，或对动态响应有一定要求的负载供电。
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本设计是获得2017电子设计大赛B题一等奖的滚球控制系统，该设计运用ov7725摄像头，oled显示图像，动态分段pid控制两个舵机，从而实现小球的运动。滚球控制系统是一个复杂的非线性动力学系统，是经典控制对象球杆系统的扩展，同时也可以作为一种具有典型非线性特征的试验平台，可以对非线性控制理论及控制算法进行检验。由于滚球控制系统中的多变量强耦合、参数不确定性、视觉反馈与传动机构滞后、小球与平板之间有摩擦以及外界随机干扰等一系列非线性因素的存在，给板球系统的分析与建模、控制系统设计与实现带来严峻挑战。本次设计的滚球系统以 K60 微控制器为核心控制单元，通过人眼摄像头采集小球的信息，使用动态 PID控制算法调节转向舵机的角度，实现了对小球运动速度和运动方向的双闭环控制，达到了小球的准确定位和轨迹控制。滚球控制系统视频演示：http://v.youku.com/v_show/id_XMzAxMDUyNzY2OA==.htm...滚球控制系统源码截图：
部分源码展示：/********************************************************************/#include "common.h"#include "include.h"#include "OLED.h"/*********************************************************/uint8 imgbuff[CAMERA_SIZE]; //定义存储接收图像的数组uint8 img[CAMERA_W*CAMERA_H]; //摄像头解压数组/*坐标定位数据*/uint8 x1=21,x2=40,x3=58;uint8 x4=20,x5=40,x6=59;uint8 x7=22,x8=40,x9=58;uint8 y1=10,y2=10,y3=11;uint8 y4=29,y5=29,y6=29;uint8 y7=48,y8=48,y9=47;uint8 squ_x1=30,squ_x2=50;uint8 squ_x3=30,squ_x4=50;uint8 squ_y1=20,squ_y2=20;uint8 squ_y3=40,squ_y4=40;/*白板边界初始化*/uint8 img_init_flag=0; //初始化变量uint8 img_init_x_min=0; //横轴最小值uint8 img_init_x_max=79; //横轴最大值uint8 img_init_y_min=0; //纵轴最小值uint8 img_init_y_max=59; //纵轴最大值uint8 img_x=40; //扫描横坐标10uint8 img_y=30; //扫描纵坐标uint8 ball_x=40; //球心横坐标uint8 ball_y=30; //球心纵坐标uint8 ball_x_set=22; //目标球心横坐标uint8 ball_y_set=48; //目标球心纵坐标uint8 ball_loca=1; //路径变量uint8 mission_flag=0; //任务标志uint32 mission_clock=0; //任务时钟/**********************舵机******************************//*动态 D*/uint8 KD_zone=2;uint32 KD_max=500,KD_min=200; //动态 D/*PID*/uint32 KP_A=10,KP_B=140,KD_X,KD_Y;//舵机 PID/*死区控制*/uint32 DJ_zone=0; //死区控制/*摆幅限制*/uint32 DJ_min=700; //舵机最小摆幅uint32 DJ_max=3000; //舵机最大摆幅/*舵机中值*/uint32 DJ_midpoint_x=8200; //舵机中值 xuint32 DJ_midpoint_y=8374; //舵机中值 y/*舵机变量*/uint64 DJ_x_PWM=8300; //输出 PWMuint64 DJ_y_PWM=8374; //输出 PWMuint32 DJ_maxpoint_x=2000; //舵机限幅_xuint32 DJ_maxpoint_y=2000; //舵机限幅_y/*******************************************************/
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2017 年 07 月 19日
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6折折扣劵只能购买小于100元（含100元）的电路。From Wikipedia, the free encyclopedia
Skylake is the
for a processor
that was launched in August 2015 succeeding the
microarchitecture. Skylake is a microarchitecture redesign using the same
as its predecessor Broadwell, serving as a "tock" in Intel's "" manufacturing and design model. According to Intel, the redesign brings greater CPU and
performance and reduced power consumption. Skylake CPUs share its microarchitecture with Kaby Lake, Coffee Lake and Cannon Lake CPUs.
Skylake is the last Intel platform on which Windows earlier than
will be officially supported by , although enthusiast-created
exist that allow
and earlier to continue to receive updates on later platforms.
Some of the processors based on the Skylake microarchitecture are marketed as "6th-generation Core".
Skylake's development, as with processors such as , , ,
and , was primarily undertaken by Intel Israel at its engineering research center in . The Haifa development team worked on the project for four years, and faced many challenges: "But by re-writing the microarchitecture and developing new concepts such as the Speed Shift Technology, we created a processor for 4.5 W to 45 W mobile devices, and up to 91 W for desktop devices." The Skylake processors will be used to power a wide range of devices, from
and tablets, all the way to desktops. "Because of Skylake's features, companies will be able to release laptop PCs that are half as thick and half as heavy as those from five years ago," according to Intel.
In September 2014, Intel announced the Skylake microarchitecture at the
in , and that volume shipments of Skylake CPUs were scheduled for the second half of 2015. Also, the Skylake development platform was announced to be available in Q1 2015. During the announcement, Intel also demonstrated two computers with desktop and mobile Skylake prototypes: the first was a desktop
system, running the latest version of , while the second computer was a fully functional laptop, playing
An initial batch of Skylake CPU models (6600K and 6700K) was announced for immediate availability during the
on August 5, 2015, unusually soon after the release of its predecessor, Broadwell, which had suffered from launch delays. Intel acknowledged in 2014 that moving from 22 nm (Haswell) to 14 nm (Broadwell) had been its most difficult process to develop yet, causing Broadwell's planned launch to sl yet, the 14 nm production was back on track and in full production as of Q3 2014. Industry observers had initially believed that the issues affecting Broadwell would also cause Skylake to slip to 2016, but Intel was able to bring forward Skylake's release and shorten Broadwell's release cycle instead. As a result, the Broadwell architecture had an unusually short run.
Officially Intel supported
of only the "K" and "X" versions of Skylake processors. However, it was later discovered that other "non-K" chips could be overclocked by modifying the base clock value – a process made feasible by the base clock only applying to the CPU, RAM, and integrated graphics on Skylake. Through beta UEFI firmware updates, some motherboard vendors, such as
(which prominently promoted it under the name "Sky OC") allowed the base clock to be modified in this manner.
In February 2016, however, an ASRock firmware update removed the feature. On February 9, 2016, Intel announced that it would no longer allow such overclocking of non-K processors, and that it had issued a CPU
update that removes the function. In April 2016, ASRock started selling motherboards that allow overclocking of unsupported CPUs using an external clock generator.
In January 2016, Microsoft announced that it would end support of
on Skylake processors effective July 17, 2017; after this date, only the "most critical" updates for the two operating systems would be released for Skylake users if they have been judged not to affect the reliability of the OS on older hardware, and
would be the only
platform officially supported on Skylake, as well as all future Intel CPU microarchitectures beginning with Skylake's successor .
stated that Microsoft had to make a "large investment" in order to reliably support Skylake on older versions of Windows, and that future generations of processors would require further investments. Microsoft also stated that due to the age of the platform, it would be "challenging" for newer hardware, firmware, and device driver combinations to properly run under Windows 7.
On March 18, 2016, in response to criticism over the move, primarily from enterprise customers, Microsoft announced revisions to the support policy, changing the cutoff for support and non-critical updates to July 17, 2018 and stating that Skylake users would receive all critical security updates for Windows 7 and 8.1 through the end of extended support. In August 2016, citing a "strong partnership with our OEM partners and Intel", Microsoft stated that it would continue to fully support 7 and 8.1 on Skylake through the end of their respective lifecycles. In addition, an enthusiast-created
was released that disabled the
check and allowed Windows 8.1 and earlier to continue to be updated on this and later platforms.
As of Linux kernel 4.10, Skylake mobile power management is in reasonably good shape with most Package C states supported seeing some use. If this is not the case, then the cause is likely bugs in the system firmware of the particular computer, which might be resolved by updating the BIOS. The user can easily optimize power management beyond the Linux default settings with the
utility and its
service, which will start up with the computer and auto-tune various settings to reduce power usage. Linux 4.11 enables Frame-Buffer Compression for the integrated graphics chipset by default, which lowers power consumption. Battery runtime should be similar to Windows 10 and possibly better, but further improvements can still be made.
version 6.1, Skylake is not supported, missing support for video acceleration amongst other things. In development versions leading up to version 6.2, at least initial support for Skylake-specific features is present.
Features[]
Top view of a Skylake i7-6700K CPU
Bottom view of a Skylake i7-6700K CPU
Like its predecessor, , Skylake is available in five variants, identified by the
"S" (SKL-S), "X" (SKL-X), "H" (SKL-H), "U" (SKL-U), and "Y" (SKL-Y). SKL-S and SKL-X contain
"K" and "X" variants with . The H, U and Y variants are manufactured in
(BGA) packaging, while the S and X variants are manufactured in
(LGA) packaging using a new socket,
( for Skylake X). Skylake is used in conjunction with , also known as Sunrise Point.
The major changes between the Haswell and Skylake architectures include the removal of the
(FIVR) introduced with Haswell. On the variants that will use a discrete
(DMI) 2.0 is replaced by , which allows speeds of up to 8 /s.
Skylake's U and Y variants support one
slot per channel, while H and S variants support two DIMM slots per channel. Skylake's launch and sales lifespan occur at the same time as the ongoing
market transition, with
memory gradually being replaced by
memory. Rather than working exclusively with DDR4, the Skylake microarchitecture remains
by interoperating with both types of memory. Accompanying the microarchitecture's support for both memory standards, a new SO-DIMM type capable of carrying either DDR3 or DDR4 memory chips, called , was also announced.
Skylake's few P variants have a reduced on-die graphics unit (12 exections units enabled instead of 24 execution units) over their direct counterparts, see the table below. In contrast, with Ivy Bridge CPUs the P suffix was used for CPUs with completely disabled on-die video chipset.
Other enhancements include , ,
graphics with  12_1 with up to 128 MB of L4
cache on certain SKUs. The Skylake line of processors retires
support, while supporting up to five monitors connected via HDMI 1.4, DisplayPort 1.2 or Embedded DisplayPort (eDP) interfaces. HDMI 2.0 (@60 Hz) is only supported on motherboards equipped with Intel’s Alpine Ridge Thunderbolt controller.
The Skylake instruction set changes include
(Memory Protection Extensions) and
(Software Guard Extensions). Future Xeon variants will also have
3.2 ("AVX-512F").
Skylake-based laptops may use wireless technology called
for charging, and other wireless technologies for communication with peripherals. Many major PC vendors have agreed to use this technology in Skylake-based laptops, which should be released by the end of 2015.
The integrated GPU of Skylake's S variant supports on Windows  12 Feature Level 12_1,  4.5 with latest Windows 10 driver update (OpenGL 4.5 on Linux) and  2.0 standards, as well as some modern hardware
formats such as
(GPU accelerated decode only),
(hardware accelerated 8-bit encode/decode and GPU accelerated 10-bit decode).
Intel also released unlocked (capable of overclocking) mobile Skylake CPUs.
Unlike previous generations, Skylake-based Xeon E3 no longer works with a desktop chipset that supports the same socket, and requires either the C232 or the C236 chipset to operate.
Short loops with a specific combination of instruction use may cause unpredictable system behavior on CPUs with hyperthreading. A
update was issued to fix the issue.
Skylake is vulnerable to
attacks. In fact, it is more vulnerable than other processors because it uses indirect branch speculation not just on indirect branches but also when the return prediction stack underflows.
The pause latency has been increased dramatically, which can cause issues with older programs or libraries using pause instructions.
Improved front-end, deeper out-of-order buffers, improved , more execution units (third vector integer (VALU)) for five ALUs in total, more load/store , improved
(wider retirement), speedup of AES-GCM and AES-CBC by 17% and 33% accordingly.
manufacturing process
socket for mainstream desktop processors and
socket for enthusiast gaming/workstation "X-Series" processors
100 Series chipset ()
"X" Series uses X299 series chipset
(TDP) up to 95 W (LGA 1151); up to 165 W (LGA 2066)
Support for both
in mainstream variants, using custom
SO-DIMM form factor with up to 64  of
on LGA 1151 variants. Usual
memory is also supported by certain motherboard vendors even though Intel doesn't officially support it.
Support for 16
3.0 lanes from CPU, 20
3.0 lanes from PCH (LGA 1151), 44
3.0 lanes for Skylake-X
Support for
(Alpine Ridge)
64 to 128 MB L4
cache on certain SKUs
Up to four cores as the default mainstream configuration and up to 18 cores for X-series
: F, CD, VL, BW, and DQ for some future Xeon variants, but not Xeon E3
(Memory Protection Extensions)
(Software Guard Extensions)
Intel Speed Shift
Skylake's integrated
supports Direct3D 12 at the
Full fixed function
Main/8bit encoding/decoding acceleration. Hybrid/Partial HEVC Main10/10bit decoding acceleration.
encoding acceleration for resolutions up to 16,000×16,000 pixels. Partial
encoding/decoding acceleration.
The L1 cache for all Skylake CPUs consists of two parts: data and instructions, whereas the former is equal to 32KB times the number of cores, and the latter is calculated the same way. So, e.g. for a six core model it will be equal to 32*6 + 32*6 = 384KB.
Skylake processors are produced in five main families: Y, U, H, S, and X. Multiple configurations are available within each family:
 Y 
 U 
 H 
 S 
 X 
Integrated L4
mobile/embedded systems
DDR3L SDRAM
DDR4 SDRAM
128 GB of physical RAM
28 to 44 PCIe 3.0 lanes
Common features of the mainstream desktop Skylake CPUs:
interfaces
Dual channel memory support in the following configurations: DDR3L- V (32 maximum) or DDR4- V (64GiB maximum). DDR3 is unofficially supported through some motherboard vendors
The Core-branded processors support the AVX2 instruction set. The Celeron and Pentium-branded ones support only SSE4.1/4.2
350 MHz base graphics clock rate
Common features of the high performance Skylake-X CPUs:
Quad channel memory support for DDR4-2400 or DDR4-2666 up to 128GiB
In addition to the AVX2 instruction set, they also support the
instructions
No built-in iGPU (integrated graphics processor)
Turbo Boost Max Technology 3.0 for up to 2/4 threads workloads for CPUs that have 8 cores and more (7820X, 7900X, 7920X, 7940X, 7960X, 7980XE)
A different cache hierarchy (in comparison to mainstream Skylake CPUs)
branding and model
clock rate
clock rate
Enthusiast/
Core i9
September 25,
August 28, 2017
June 19, 2017
Core i7
Mainstream
4.0 GHz
4.2 GHz
HD 530
August 5, 2015
3.3 GHz
3.9 GHz
3.8 GHz
3.5 GHz
Iris Pro 580
May 3, 2016
3.4 GHz
4.0 GHz
3.9 GHz
3.7 GHz
September 1, 2015
2.8 GHz
3.6 GHz
3.5 GHz
3.4 GHz
3.5 GHz
3.9 GHz
3.8 GHz
3.6 GHz
August 5, 2015
3.2 GHz
3.8 GHz
3.7 GHz
3.3 GHz
Iris Pro 580
May 3, 2016
3.3 GHz
3.9 GHz
3.8 GHz
3.6 GHz
September 1, 2015
2.8 GHz
3.6 GHz
3.5 GHz
3.1 GHz
Iris Pro 580
May 3, 2016
3.2 GHz
3.3 GHz
September 1, 2015
2.7 GHz
3.5 GHz
3.4 GHz
3.3 GHz
2.5 GHz
3.1 GHz
3.0 GHz
2.8 GHz
2.8 GHz
3.4 GHz
3.4 GHz
3.2 GHz
HD 510
0950 MHz
December 27, 2015
2.2 GHz
2.8 GHz
2.7 GHz
2.5 GHz
HD 530
2.7 GHz
3.3 GHz
3.3 GHz
3.1 GHz
August 5, 2015
Core i3
3.9 GHz
3.8 GHz
3.7 GHz
October 2015
3.3 GHz
0950 MHz
3.2 GHz
3.6 GHz
HD 510
December 27, 2015
3.6 GHz
HD 530
October 2015
3.5 GHz
3.0 GHz
0950 MHz
3.3 GHz
HD 510
October 2015
2.9 GHz
0950 MHz
2.4 GHz
2.9 GHz
2.8 GHz
2.3 GHz
2.6 GHz
See also "Server, Mobile" below for mobile workstation processors.
branding and
clock rate
GPU clock rate
Release date
Price (USD)
Performance
4 (8)
Core i7
2.8 GHz
3.7 GHz
Iris Pro 580
350 MHz
128 MB
2.9 GHz
3.8 GHz
3.6 GHz
3.4 GHz
HD 530
September 1, 2015
2.7 GHz
3.6 GHz
Iris Pro 580
128 MB
3.4 GHz
3.2 GHz
HD 530
September 1, 2015
2.6 GHz
3.5 GHz
Iris Pro 580
950 MHz
128 MB
3.3 GHz
3.1 GHz
HD 530
September 1, 2015
Mainstream
2 (4)
2.4 GHz
3.4 GHz
3.2 GHz
Iris 540
300 MHz
64 MB
9.5 W
2.2 GHz
2.6 GHz
HD 520
7.5 W
September 1, 2015
3.3 GHz
3.6 GHz
3.4 GHz
Iris 550
64 MB
2.2 GHz
3.2 GHz
3.1 GHz
Iris 540
9.5 W
2.5 GHz
3.1 GHz
3.0 GHz
HD 520
7.5 W
September 1, 2015
4 (4)
Core i5
2.6 GHz
3.5 GHz
3.3 GHz
3.1 GHz
HD 530
350 MHz
950 MHz
2 (4)
2.0 GHz
3.1 GHz
2.9 GHz
Iris 540
300 MHz
64 MB
9.5 W
4 (4)
2.3 GHz
3.2 GHz
Iris Pro 580
350 MHz
900 MHz
128 MB
3.0 GHz
2.8 GHz
HD 530
950 MHz
September 1, 2015
2 (4)
2.4 GHz
3.0 GHz
2.9 GHz
HD 520
300 MHz
7.5 W
3.1 GHz
3.5 GHz
3.3 GHz
Iris 550
64 MB
2.9 GHz
3.3 GHz
3.1 GHz
1.8 GHz
2.9 GHz
2.7 GHz
Iris 540
950 MHz
9.5 W
2.3 GHz
2.8 GHz
HD 520
7.5 W
September 1, 2015
Core i3
2.7 GHz
Iris 550
64 MB
2.4 GHz
2.7 GHz
HD 530
350 MHz
900 MHz
September 1, 2015
2.3 GHz
HD 520
300 MHz
7.5 W
2.0 GHz
900 MHz
November, 2016
Core m7
1.2 GHz
3.1 GHz
2.9 GHz
HD 515
300 MHz
4.5 W
3.5 W
September 1, 2015
Core m5
1.1 GHz
2.8 GHz
2.4 GHz
900 MHz
2.7 GHz
Core m3
0.9 GHz
2.2 GHz
2.0 GHz
850 MHz
3.8 W
2.1 GHz
950 MHz
1.5 GHz
800 MHz
4.5 W
2 (2)
1.6 GHz
350 MHz
950 MHz
2.4 GHz
2.0 GHz
300 MHz
900 MHz
1.6 GHz
All models support: , , , , , , , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , ,
(excluding W-2102 and W-2104),
(excluding W-2102 and W-2104), , , Smart Cache.
PCI Express lanes: 48
Supports up to 8 DIMMs of DDR4 memory, maximum 512 GB.
all-core/2.0
(/max. 3.0)
Release date
SR3LG (U0)
4 × 1 MiB
120 W
4 × DDR4-2400
29 August 2017
SR3LH (U0)
4 × 1 MiB
120 W
4 × DDR4-2400
29 August 2017
SR3LJ (U0)
4 × 1 MiB
120 W
4 × DDR4-2666
29 August 2017
SR3LM (U0)
4 × 1 MiB
120 W
4 × DDR4-2666
29 August 2017
SR3LL (U0)
6 × 1 MiB
140 W
4 × DDR4-2666
29 August 2017
SR3LN (U0)
6 × 1 MiB
140 W
4 × DDR4-2666
29 August 2017
Xeon W-2140B
8 × 1 MiB
4 × DDR4-2666
OEM for Apple
SR3LQ (U0)
8 × 1 MiB
140 W
4 × DDR4-2666
29 August 2017
Xeon W-2150B
10 × 1 MiB
4 × DDR4-2666
OEM for Apple
SR3LR (U0)
10 × 1 MiB
140 W
4 × DDR4-2666
29 August 2017
SR3W2 (M0)
14 × 1 MiB
140 W
4 × DDR4-2666
15 October 2017
SR3RX (U0)
18 × 1 MiB
140 W
4 × DDR4-2666
29 August 2017
E3 series server chips all consist of System Bus 9 GT/s, max. memory bandwidth of 34.1 GB/s dual channel memory. Unlike its predecessor, the Skylake Xeon CPUs require either a C232 or a C236 chipset to operate.
Skylake E3-12xx and E3 15xx v5 SKUs
branding and model
price (USD)
tray / box
Motherboard
4 (8)
3.7 GHz
4.0 GHz
$612 / —
3.6 GHz
350 MHz
1.15 GHz
$339 / —
3.6 GHz
$328 / $339
2.9 GHz
3.9 GHz
$294 / —
3.5 GHz
350 MHz
1.15 GHz
$284 / —
3.5 GHz
$272 / $282
2.1 GHz
3.2 GHz
$278 / —
3.4 GHz
3.8 GHz
$250 / $260
4 (4)
2.0 GHz
3.0 GHz
350 MHz
1.15 GHz
$250 / —
3.3 GHz
3.7 GHz
$213 / —
3.0 GHz
3.5 GHz
$193 / —
4 (8)
Iris Pro 580
3.0 GHz
3.9 GHz
350 MHz
1.1 GHz
128 MB
$1207 / —
LPDDR3-1866
DDR3L-1600
2.9 GHz
3.8 GHz
1.05 GHz
$679 / —
$623 / —
2.8 GHz
3.7 GHz
$434 / —
2.0 GHz
2.8 GHz
1.0 GHz
$433 / —
"Skylake-SP" (14 nm) Scalable Performance[]
Xeon Platinum supports up to 8 sockets. Xeon Gold supports up to 4 sockets. Xeon Silver and Bronze support up to 2 sockets.
-M: ;GB RAM per socket instead of 768 GB RAM for non-M SKUs
-F: integrated OmniPath fabric
-T: High thermal-case and extended reliability
Support for up to 12
memory per CPU socket.
Xeon Platinum, Gold 61XX, and Gold 5122 have two
FMA units per core. Xeon Gold 51XX (except 5122), Silver, and Bronze have a single
FMA unit per core.
Xeon Bronze 31XX has no HT or Turbo Boost support.
Xeon Bronze 31XX supports DDR4-;MHz RAM. Xeon Silver 41XX supports DDR4-;MHz RAM.
Xeon Bronze 31XX and Xeon Silver 41XX support two UPI links at 9.6 GT/s.
all-core/2.0
(/max. 3.0)
Release date
SR3GM (U0)
6 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2133
11 July 2017
SR3GL (U0)
8 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2133
11 July 2017
SR3GJ (U0)
2.1/3.0 GHz
8 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GP (U0)
2.3/3.0 GHz
8 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GH (U0)
2.4/3.0 GHz
8 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GN (U0)
2.9/3.0 GHz
4 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GK (U0)
2.5/3.0 GHz
10 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3MM (U0)
2.5/3.0 GHz
10 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
SR3HQ (M0)
2.4/3.0 GHz
12 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3MQ (U0)
2.4/3.0 GHz
12 × 1 MiB
2 × 9.6 GT/s UPI
6 × DDR4-2400
Xeon Gold 51XX has two UPIs at 10.4 GT/s. Xeon Gold 61XX has three UPIs at 10.4 GT/s.
Xeon Gold 51XX support DDR4-;MHz RAM (except 5122). Xeon Gold 5122 and 61XX support DDR4-;MHz RAM.
all-core/2.0
(/max. 3.0)
Release date
SR3GB (M0)
2.8/3.2GHz
10 × 1 MiB
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
2.3/2.8GHz
14 × 1 MiB
105 W
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
2.3/2.8GHz
14 × 1 MiB
113 W
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GF (M0)
2.7/3.2GHz
12 × 1 MiB
105 W
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3MN (M0)
2.3/3.2GHz
14 × 1 MiB
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GD (M0)
2.6/3.2GHz
14 × 1 MiB
105 W
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3GC (M0)
2.6/3.2GHz
14 × 1 MiB
105 W
2 × 10.4 GT/s UPI
6 × DDR4-2400
11 July 2017
SR3AT (H0)
3.7/3.7GHz
4 × 1 MiB
105 W
2 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B3 (H0)
3.3/3.7GHz
12 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3KE (H0)
3.3/3.7GHz
12 × 1 MiB
135 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J9 (H0)
3.3/3.7GHz
12 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J4 (H0)
3.7/3.7GHz
6 × 1 MiB
115 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B9 (H0)
2.8/3.7GHz
16 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3KD (H0)
2.8/3.7GHz
16 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J8 (H0)
2.8/3.7GHz
16 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J3 (H0)
3.3/3.7GHz
14 × 1 MiB
140 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3AR (H0)
3.7/3.7GHz
8 × 1 MiB
130 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3AS (H0)
3.7/3.7GHz
8 × 1 MiB
130 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B2 (H0)
3.6/3.7GHz
12 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B5 (H0)
2.7/3.7GHz
20 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3KK (H0)
2.7/3.7GHz
20 × 1 MiB
135 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J7 (H0)
2.7/3.7GHz
20 × 1 MiB
125 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3AX (H0)
3.0/3.7GHz
18 × 1 MiB
140 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3AZ (H0)
3.0/3.7GHz
18 × 1 MiB
140 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3AY (H0)
3.3/3.7GHz
16 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3KH (H0)
3.3/3.7GHz
16 × 1 MiB
160 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B1 (H0)
3.3/3.7GHz
16 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3MB (H0)
4.1/4.2GHz
8 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
Xeon Gold 6145
SR3G4 (H0)
2.7/3.7GHz
20 × 1 MiB
145 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR3MA (H0)
3.9/4.2GHz
12 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B6 (H0)
3.1/3.7GHz
20 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3KJ (H0)
3.1/3.7GHz
20 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
Xeon Gold 6149
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR37K (H0)
3.4/3.7GHz
18 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B4 (H0)
2.8/3.7GHz
22 × 1 MiB
140 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J5 (H0)
3.7/3.7GHz
18 × 1 MiB
200 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
Xeon Gold 6161
SR3G7 (H0)
2.7/3.0GHz
22 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
Xeon Platinum has three UPIs at 10.4 GT/s.
Xeon Platinum supports DDR4-;MHz RAM.
all-core/2.0
(/max. 3.0)
Release date
SR3BA (H0)
2.3/2.8 GHz
125 W
3 × 10.4 GT/s
6 × DDR4-2666
11 July 2017
SR3AV (H0)
3.3/3.7 GHz
4 × 1 MiB
105 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B7 (H0)
2.7/3.7 GHz
12 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B0 (H0)
2.8/3.7 GHz
24 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B8 (H0)
2.8/3.7 GHz
24 × 1 MiB
160 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3B8 (H0)
2.8/3.7 GHz
24 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3J6 (H0)
2.8/3.7 GHz
24 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
Xeon Platinum 8163
SR3G1 (H0)
2.7/3.1 GHz
24 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR3BB (H0)
2.7/3.7 GHz
26 × 1 MiB
150 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
Xeon Platinum 8167M
SR3A0 (H0)
2.4/2.4 GHz
26 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR37J (H0)
3.4/3.7 GHz
24 × 1 MiB
205 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR37H (H0)
2.8/3.7 GHz
26 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3BD (H0)
2.8/3.7 GHz
26 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
Xeon Platinum 8173M
SR37Q (H0)
2.7/3.5 GHz
28 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR37A (H0)
2.8/3.8 GHz
28 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR3MK (H0)
2.8/3.8 GHz
28 × 1 MiB
173 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
SR37U (H0)
2.8/3.8 GHz
28 × 1 MiB
165 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR377 (H0)
3.2/3.8 GHz
28 × 1 MiB
205 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
SR37T (H0)
3.2/3.8 GHz
28 × 1 MiB
205 W
3 × 10.4 GT/s UPI
6 × DDR4-2666
11 July 2017
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Intel CPU core roadmaps from
Feature size
(166–200 MHz)
NetBurst()
reintroduced, integrated , ,
L3-cache introduced, 256KiB L2-cache/core,
on same package in 45nm,
introduced
Sandy Bridge
on-die ring bus, GPU on , no more non- motherboards,
Silvermont
or 10 nm++
Ice Lake or new architecture
Italic names indicate canceled processors
Bold names are the microarchitecture names
Bold italic names are future processors
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