Current reference with Nwell resistor and poly resistor
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Member level 4
Current reference with Nwell resistor and poly resistor
In order to design a temperature indepedent current reference with bandgap reference, I want to combine a Nwell resistor(positive temperature coefficient) and
a poly reisitor(nagative temperature coefficient). The simulation results are really good, but I am not sure the real results after type out. Anyone who had such a experience of combination of differenct type of resistors please give me some advice? Or tell me some drawbacks about this combination? Any comments are welcome. Thanks in advance.
Member level 4
Current reference with Nwell resistor and poly resistor
I have not used the combination you are trying to implement. n-well resistor will have a back bias coefficient which simulation ignores.
one has to hand calculate its effects and select the proper size resistors during the layout.
Member level 4
Re: Current reference with Nwell resistor and poly resistor
According to the spice modle, after hand calculation, the leakage current is less than 1E-9A. The spec of the current reference is 10E-6A, so I think the back bias effect can be ignored.
Advanced Member level 3
Current reference with Nwell resistor and poly resistor
try monter-carlo analysis
Full Member level 4
Re: Current reference with Nwell resistor and poly resistor
From process point of view, this is not a bad idea at all.
Other than back bias and parasitic cap which are always to be watched
using Nwell resisitance.
One more thing to mention, this may very from fab to fab,
but the variation in resistance /per square is generally
(one sigma, including die to die base, and lot to lot base)
~5%. And that may degrade the cancellation of the temp coef.
Member level 2
Current reference with Nwell resistor and poly resistor
you know the simu results good cann't see the tape out test results is good . pls take care of the error in layout and technology.
Member level 5
Achievements:
Re: Current reference with Nwell resistor and poly resistor
Hi Lunren,
I think you can do, whatever you are thinking
Full Member level 1
Re: Current reference with Nwell resistor and poly resistor
I have seen this technique before on TSMC0.25u fab, and it worked just fine.
We didn't need to worry about the nwell back voltage at all, the sim results were very close the the testing results.
So I suggest you go on.
Full Member level 6
Current reference with Nwell resistor and poly resistor
I've done so in one of my design, results i obtain only in september. But now it's seems to me it isn't good idea. It may suffer from the reason that parameters of diff. resistor varied during tech.process not simultaineously with parameters of poly. resistor. If after manufacturing u'll get different corners for diff. & poly. resistors u don't get full temp. compensation i think. Try to simulate with different corners models for diff. & poly. resistors. If results will meet specification use such technique.
Newbie level 5
Current reference with Nwell resistor and poly resistor
but different resistor process may produce mismatches that can't be ignored
Full Member level 6
Current reference with Nwell resistor and poly resistor
In additional one more idea. If connect diode in series with resistors (with proper choice device parameters) than it's possible to correct nonlinearity of bandgap output voltage to get temp. independent current.
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, , , , , , , , ,0.35um CMOS process
<h1 id="hl.35um CMOS process (C35)
ams' 0.35um CMOS process family is fully compatible to the 0.35um mixed signal base process licensed from TSMC. The high density CMOS standard cell library optimized for synthesis and 3- and 4-layer routing guarantees highest gate densities. Peripheral cell libraries are available for 3.3V and 5.0V with high driving capabilities and excellent ESD performance. Qualified digital macro blocks (RAM, diffusion programmable ROM and DPRAM) are available on request. A variety of high performance analog-to-digital and digital-to-analog converters can be provided for integration on the same IC.
The industry leading design environment (hitkit) includes silicon-qualified digital, analog and RF library elements and a complete set of low voltage devices (3.3V and 5.0V). Fully characterized simulation models including noise, matching and parasitic elements, extraction and verification run sets as well as automatic layout device generators complete the C35 hitkit offering.&Hence product developers&are enabled with a plug-and-play tool set which facilitates &first time right& designs.&
Applications&& markets:
Digital, Analog and Mixed Signal Systems, sensors and sensor solutions
Consumer & Communications, Automotive, Industrial, Medical, Space, Aerospace
Highlights
Operating voltages from 3.3V to 5.0V
Compatible to TSMC's 0.35um CMOS&process allowing IP reuse
3-4&metal levels
Fully characterized set of passive devices including various capacitors and high res. poly
Extensive primitive device library
ESD protection cells with up to 8kV HBM level available
Industry leading design environment (hitkit) including
automatic layout device generators (PCELLs)
various digital and analog standard cells
highly accurate simulation models including noise, matching and parasitics
full verification support (Safe Operating Area Check tool, DRC, LVS, RC-extract)
Key technology features
Technology node: 0.35um polycide
Levels of metal: 3-4
Metallization: Al
Dielectric: SIO2
Gate density: 17k / 23k Gates/mm?
Maximum operating voltages of NMOS & PMOS: 3.3V&or 5.0V
Device overview
LV CMOS Devices:
Low voltage MOS transistors (3.3V gates): NMOS, PMOS
Low voltage MOS transistors (5,0V gates): NMOSM, PMOSM
Low VT Devices:&
Low voltage VT&MOS transistors (3.3V gates): NMOSL, PMOSL
Low voltage VT MOS transistors (5,0V gates): NMOSML, PMOSML
Resistors:
NWELL resistor
Diffusion resistor (N+, P+)&
Poly1 resistor (P+)
High resistive poly
Capacitors:
Poly-MIM stacked capacitor
Library overview
CORELIB:&3.3V digital standard cells
CORELIB: 5.0V digital standard cells
CORELIB_D:&3.3V digital standard cells, high density
CORELIB_D 3-bus: 3.3V digital standard cells, high density, 3-bus
CORELIB_D 3-bus: 5.0V digital standard cells, high density, 3-bus
IOLIB_3M:&Digital peripheral cells, 3 metal
IOLIB_3B_3M: Digital peripheral cells,&3 metal, 3-bus, 3.3V
IOLIBV5_3M: Digital peripheral cells, 3 metal, 5.0V
IOLIBC_3B_3M: Core limited digital peripheral cells, 3 metal, 3.3V
IOLIBCV5_3B_3M: Core limited digital peripheral cells, 3 metal, 5.0V
IOLIB_4M: Digital peripheral cells,&4 metal
IOLIB_3B_4M: Digital peripheral cells, 4 metal, 3-bus, 3.3V
IOLIBV5_4M: Digital peripheral cells,&4 metal, 5.0V
IOLIBC_3B_4M: Core limited digital peripheral cells,&4 metal, 3.3V
IOLIBCV5_3B_4M: Core limited digital peripheral cells,&4 metal, 5.0V
&IP block overview
Digital IP:
High density digital core library (23 Kgates/mm?), 3.3V
High density digital core library (23Kgates/mm?), 3-bus, 3.3V
Polyfuse based OTP
RAM memory compiler
ROM memory compiler
Analog IP:
Flash6.C35:
SCADC12F.C35:
ADC1020.C35:
ADC1220.C35:
CDAC10.C35:
CDAC12.C35:
LVDS-TX.C35:
LVDS-RC.C35:
PECL-TX.C35:
PECL-RX.C35:
Microcontroller:
ARM Cortex available on request
Other IP blocks:
ams cooperates with industry recognized IP providers and third party design houses who offer silicon-proven IP blocks off the shelf as well as individually designed custom IP blocks.
A complete overview of analog IP blocks available in
&hitkit description
The ams hitkit for C35 process has been qualified for Cadence IC 6.1.5. Please visit our foundry support server in order to learn more about the hitkit for C35 process. Note: Access to the information below requires an NDA with ams and
on our foundry support server.
hitkit v4.10&related
Supported environment
Cadence IC 6.1
Ultrasim MMSIM
RTL Compiler
Synopsys Design Compiler
IUS/AMS-Designer
Encounter EDI
Assura DRC/LVS
Calibre DRC/LVS
Manufacturing & foundry logistics
Wafer size: 200mm / 8 inch
Number of mask levels: 13 masks minimum
Minimum lot size - engineering:&6 wafers
Minimum lot size - production: 25 wafers
Hot-lot availability: Yes, availability to be confirmed by foundry at start of production
MPW availability: Yes, minimum 1 run per quarter (please refer to
available on our foundry support server)
Manufacturing lead times: Available on request, please contact your .
&&&&&&&&&&&&&&poly电阻下面添加p+是做什么用的?
只有P+ OD电阻放在NWELL中,nwell接VDD做 shielding.如果要干净一点,放在衬底上,周围围ring接到VSS,防止被周围电路干扰.
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