MT-E701 ADC DAC精度测试
& & & & Copyright (C) 2016 mangotree.cn All Rights Reserved.& & & & & & & &电话：1&&&&&&&&&邮箱： ，
& & & & & 微博：芒果树技术 & & & & & & & & & 微信公众号：芒果树技术微笑和Uzi到底谁是中国第一ADC？看看当事人怎么说
[摘要]这是一个长盛不衰的、见仁见智的、非常容易引起互喷的话题，就好比NBA的科比詹姆斯和乔丹的对比。谁是中国第一ADC？如果你只是不负责任的甩出一句没有可比性之类话语，那也就不用再勉为其难的看下去了。毕竟同为职业选手，他们的表现、数据以及其他种种都能很清晰的展现在我们面前，不妨客观的拿来做一次跨越时间的对比。当然，因为没办法来个直接的ONE BY ONE（双人路本身也没有纯粹的单挑之说），并且所处年代、版本、对手的实力也都有差异，所以一概而论的定性也是牵强的，只能分开来单独比较，做一个全面的比较。先来看看当事人彼此的评价Uzi：微笑是我碰到过的最强的ADC（提问：你觉得谁是LPL里你遇到最强的对手）微笑：UZI是第一ADC（S4世界总决赛期间微笑接受采访时表示）彼此都给了对方最高的评价，可以说是惺惺相惜，想从他们嘴里听到到底谁强的回答显然是不可能的。1--成绩 （Uzi 0：2 微笑）这一项微笑暂时领先（因为Uzi还没退役，一切也皆有可能）。到目前为止Uzi没有拿到过一次大赛冠军，微笑单单一次IPL5冠军就已经算是赢了。虽然我认为两次S系列赛亚军也很有含金量，虽然我是狗粉，但这就是竞技比赛的对比，很残酷，只有冠军会被记住，而且当年We战队在全世界范围内的影响与口碑也不是现在任何一支LPL队伍能比的。所以这一比微笑赢，而且是两分。2--心理状态 （Uzi 0：3 微笑）心理状态对于一名AD选手来说是最重要的。抗压能力，调整能力，顺风时情绪的控制以及逆风时坚定的信念等等都在其中。其实这一条我认为都算是这两名选手的强项，尤其是到了国际大赛，他们都能展现出超强的抗压能力从而发挥出自己真正的实力，也都拥有绝对的自信。唯一稍显不足的就是Uzi在逆风局的处理上还有待提高，自己或者队友的失误都能够影响到小狗的情绪，历来小狗所在的队伍的比赛多数都是一边倒的局势，少有逆风翻盘就能看出一二。而微笑在这一点上可以算是比较完美的了，不管是比赛中还是后来的直播里，很少看到他情绪的波动，哪怕是崩了也会很耐心的寻找发育空间来尽量延长比赛争取逆转。所以在这一项对比中，微笑依然领先，但我们也看到了小狗的成长，希望他之后能够更好。3--个人能力（Uzi 1：3 微笑）这一项比较复杂，需要对比的也比较多。操作（天赋）：Uzi>微笑。这一点拿出录像看一看就自然有结果了，两个选手操作都很强，无缝走A，技能的运用以及对敌方技能的预判等等都是超一流的，但是如果对比技能衔接的速率，细小走位的反应以及对伤害的计算等细节上来讲，Uzi确实要高出微笑一筹，他这方面的天赋也是被广泛认可的。所以这一项上小狗领先。线上能力：Uzi≈微笑。这个问题就要考虑一下客观环境了，微笑所处的年代游戏算是起步初期，选手对于游戏的理解、比赛中的对抗强度以及国外对手的实力都不能与今天相提并论了，直接对比不能算是客观，只能说他们都在各自的年代诠释了什么叫做压制力，同样的补发育能力也都很强，所以算是平手。团战能力：Uzi≈微笑。小狗的团战更多的是依靠超强的操作能力来打出爆炸伤害，同时依赖队友的保护来为他降低偶尔的激进所带来的风险，无论什么版本都基本保持在全队输出占比第一位上。而微笑则相对内敛，无需队友过多的照顾，依靠个人的走位安全输出，给了其他位置更多的发挥空间。只能说风格不同，同样是大腿，同样输出爆炸，平分综合起来看，小狗在操作方面的优势使他在个人能力一项上的对比扳回一分。4--大环境对比（Uzi 2：3微笑）巅峰微笑所处在的版本正好是LOL发展至今少有的依靠AD左右比赛胜负的版本，AD位置更容易将优势直接转化成了队伍的胜利，再加上韩国那时候的LOL还没步入正轨，少了这么一个强大的敌人，他的成绩值得骄傲但还算是情理之中。而Uzi悖逆着版本，面对着更多更加强大的对手依然打出今天的成绩，难度确实比微笑更高。Uzi再加一分5--影响力（Uzi 3：3微笑）这一点小狗占了先天优势，毕竟随着职业化的发展，现如今LOL这款游戏的影响力以及受关注度已不是早年微笑的时代可比。所谓影响力也是面对受众群体来说的，现在的粉丝数量多，曝光度高，再加上随着竞争越来越激烈选手们承载了更多希望，影响力上势必盖过早期的职业选手。6--未来（Uzi 4;3微笑）现役的对比退役，终归还是多了一个希望，还有无数的可能。总结，单独讲两个人绝对是各有千秋，但是以一位职业选手的标准综合起来评判的话，小狗可以说已经算是目前为止最为成功出色ad选手了。强于微笑，但他的路不止在LPL，希望有朝一日能在最能体现职业选手实力的成绩一栏留下他的一笔！
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Copyright & 1998 - 2018 Tencent. All Rights ReservedSTM32 ADC三重采样的坑 – TaterLi 个人博客
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三重采样很简单,就是三个ADC叠加成更高速度,但是不是所有通道都支持三重采样.如图,只有写着ADC123_INx的才可以.
当初改掉原来官方的ADC1 + ADC2接PA4结果什么用都没,真是麻烦.另外只能按照WORD传输.进入DMA中断后要赶紧处理数据.取出高16和低16位.这个三重下,顺序是比较复杂(其实也就是先来后到),不过实际上不用管,当做只有一个ADC在工作就好了.
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
aADCyMultimodeDualSlaveConvertedData[tmp_index]
= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
&&&&&&&&aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);&&&&&&&&aADCyMultimodeDualSlaveConvertedData[tmp_index]&&= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
得到数据该怎么处理就怎么处理,这么快速度,串口是发不走的了,因为串口至少得bps,不太可能,看看怎么送出去了,这数据.或者处理.
******************************************************************************
Examples_LL/ADC/ADC_MultimodeDualInterleaved/Src/main.c
MCD Application Team
* @version V1.0.0
30-December-2016
This example describes how to use several ADC peripherals in
multimode, mode interleaved.
ADC master instance synchronizes and manages ADC slave instance.
Multimode interleaved combines ADC instances to convert
the same channel and increase the overall ADC conversion rate.
This example configures the ADC to perform conversions at the
maximum ADC conversion rate possible (with a sampling time
corresponding to ADC resolution 12 bits).
This example is based on the STM32F7xx ADC LL API;
Peripheral initialization done using LL unitary services functions.
******************************************************************************
* @attention
* &h2&&center&(C) COPYRIGHT(c) 2016 STMicroelectronics&/center&&/h2&
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of STMicroelectronics nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/** @addtogroup STM32F7xx_LL_Examples
/** @addtogroup ADC_MultimodeDualInterleaved
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Definitions of ADC hardware constraints delays */
/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,
not timeout values:
Timeout values for ADC operations are dependent to device clock
configuration (system clock versus ADC clock),
and therefore must be defined in user application.
Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout
values definition.
/* Timeout values for ADC operations. */
/* (enable settling time, disable settling time, ...)
/* Values defined to be higher than worst cases: low clock frequency,
/* maximum prescalers.
/* Example of profile very low frequency : ADC clock frequency 36MHz
/* prescaler 2, sampling time 56 ADC clock cycles, resolution 12 bits.
- ADC enable time: maximum delay is 3 us
(refer to device datasheet, parameter "tSTAB")
- ADC disable time: maximum delay should be a few ADC clock cycles
- ADC stop conversion time: maximum delay should be a few ADC clock
- ADC conversion time: with this hypothesis of clock settings, maximum
delay will be 99us.
(refer to device reference manual, section "Timing")
/* Unit: ms
#define ADC_CALIBRATION_TIMEOUT_MS
((uint32_t)
#define ADC_ENABLE_TIMEOUT_MS
((uint32_t)
#define ADC_DISABLE_TIMEOUT_MS
((uint32_t)
#define ADC_STOP_CONVERSION_TIMEOUT_MS
((uint32_t)
#define ADC_CONVERSION_TIMEOUT_MS
((uint32_t)
/* Definitions of environment analog values */
/* Value of analog reference voltage (Vref+), connected to analog voltage
/* supply Vdda (unit: mV).
#define VDDA_APPLI
((uint32_t)3300)
/* Definitions of data related to this example */
/* Init variable out of expected ADC conversion data range */
#define VAR_CONVERTED_DATA_INIT_VALUE
(__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)
/* Definition of ADCx conversions data table size */
/* Note: Considering interruption occurring after each number of
"ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions
(IT from DMA transfer complete),
select sampling time and ADC clock with sufficient
duration to not create an overhead situation in IRQHandler.
#define ADC_CONVERTED_DATA_BUFFER_SIZE
((uint32_t) 256)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Variables for ADC conversion data */
uint32_t aADCxADCyMultimodeDualConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];
/* ADC multimode dual conversion data: ADC master and ADC slave conversion data are concatenated in a registers of 32 bits. */
static uint16_t aADCxMultimodeDualMasterConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];/* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC master conversion data. */
static uint16_t aADCyMultimodeDualSlaveConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC slave conversion data. */
/* Variable to report status of DMA transfer of ADC group regular conversions */
0: DMA transfer is not completed
1: DMA transfer is completed
2: DMA transfer has not been started yet (initial state)
__IO uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback */
/* Private function prototypes -----------------------------------------------*/
SystemClock_Config(void);
Configure_DMA(void);
Configure_ADC(void);
Configure_ADC_slave(void);
Activate_ADC(void);
Activate_ADC_slave(void);
static void CPU_CACHE_Enable(void);
/* Private functions ---------------------------------------------------------*/
Main program
* @retval None
int main(void)
/* Enable the CPU Cache */
CPU_CACHE_Enable();
/* Configure the system clock to 216 MHz */
SystemClock_Config();
/* Initialize button in EXTI mode */
/* UserButton_Init(); */
/* Configure DMA for data transfer from ADC */
Configure_DMA();
/* Configure ADC */
/* Note: This function configures the ADC but does not enable it.
To enable it, use function "Activate_ADC()".
This is intended to optimize power consumption:
1. ADC configuration can be done once at the beginning
(ADC disabled, minimal power consumption)
2. ADC enable (higher power consumption) can be done just before
ADC conversions needed.
Then, possible to perform successive "Activate_ADC()",
"Deactivate_ADC()", ..., without having to set again
ADC configuration.
Configure_ADC();
/* For multimode, configure ADC slave */
Configure_ADC_slave();
/* Activate ADC */
/* Perform ADC activation procedure to make it ready to convert. */
Activate_ADC();
Activate_ADC_slave();
LL_ADC_REG_StartConversionSWStart(ADC1);
/* Infinite loop */
/* Note: ADC group regular conversion start is done into push button
IRQ handler, refer to function "UserButton_Callback()".
/* Note: LED state depending on DMA transfer status is set into DMA
IRQ handler, refer to functions "DmaTransferComplete()"
and "DmaTransferHalfComplete()".
/* Note: ADC conversion data are stored into array
"aADCxADCyMultimodeDualConvertedData".
For this example purpose, ADC conversion data of ADC master and
ADC slave are dispatched into arrays */
"aADCxMultimodeDualMasterConvertedData"
and "aADCyMultimodeDualSlaveConvertedData", refer to comments
into function "DmaTransferComplete()".
(for debug: see variable content into watch window).
/* Note: ADC conversion data can be computed to physical values
using ADC LL driver helper macro:
uhADCxConvertedData_Voltage_mVolt
= __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI,
uhADCxConvertedData),
LL_ADC_RESOLUTION_12B)
This function configures DMA for transfer of data from ADC
* @retval None
void Configure_DMA(void)
/*## Configuration of NVIC #################################################*/
/* Configure NVIC to enable DMA interruptions */
NVIC_SetPriority(DMA2_Stream0_IRQn, 1);
/* DMA IRQ lower priority than ADC IRQ */
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
/*## Configuration of DMA ##################################################*/
/* Enable the peripheral clock of DMA */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
/* Configure the DMA transfer */
- DMA transfer in circular mode to match with ADC configuration:
DMA unlimited requests.
- DMA transfer from ADC without address increment.
- DMA transfer to memory with address increment.
- DMA transfer from ADC by word to match with ADC configuration:
ADC resolution 12 bits and and multimode enabled,
ADC master and ADC slave conversion data are concatenated in
a register of 32 bits.
- DMA transfer to memory by word to match with ADC conversion data
buffer variable type: word.
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_0, LL_DMA_CHANNEL_0);
LL_DMA_ConfigTransfer(DMA2,
LL_DMA_STREAM_0,
LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
LL_DMA_MODE_CIRCULAR
LL_DMA_PERIPH_NOINCREMENT
LL_DMA_MEMORY_INCREMENT
LL_DMA_PDATAALIGN_WORD
LL_DMA_MDATAALIGN_WORD
LL_DMA_PRIORITY_HIGH
/* Set DMA transfer addresses of source and destination */
/* Note: On this STM32 device, in multimode, ADC conversion data with
ADC master and ADC slave conversion data concatenated are located
in a specific multimode data register.
LL_DMA_ConfigAddresses(DMA2,
LL_DMA_STREAM_0,
LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA_MULTI),
(uint32_t)&aADCxADCyMultimodeDualConvertedData,
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
/* Set DMA transfer size */
LL_DMA_SetDataLength(DMA2,
LL_DMA_STREAM_0,
ADC_CONVERTED_DATA_BUFFER_SIZE);
/* Enable DMA transfer interruption: transfer complete */
LL_DMA_EnableIT_TC(DMA2,
LL_DMA_STREAM_0);
/*## Activation of DMA #####################################################*/
/* Enable the DMA transfer */
LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_0);
Configure ADC (ADC instance: ADC1) and GPIO used by ADC channels.
In case re-use of this function outside of this example:
This function includes checks of ADC hardware constraints before
executing some configuration functions.
- In this example, all these checks are not necessary but are
implemented anyway to show the best practice usages
corresponding to reference manual procedure.
(On some STM32 series, setting of ADC features are not
conditioned to ADC state. However, in order to be compliant with
other STM32 series and to show the best practice usages,
ADC state is checked anyway with same constraints).
Software can be optimized by removing some of these checks,
if they are not relevant considering previous settings and actions
in user application.
- If ADC is not in the appropriate state to modify some parameters,
the setting of these parameters is bypassed without error
reporting:
it can be the expected behavior in case of recall of this
function to update only a few parameters (which update fullfills
the ADC state).
Otherwise, it is up to the user to set the appropriate error
reporting in user application.
Peripheral configuration is minimal configuration from reset values.
Thus, some useless LL unitary functions calls below are provided as
commented examples - setting is default configuration from reset.
* @retval None
void Configure_ADC(void)
/*## Configuration of GPIO used by ADC channels ############################*/
/* Note: On this STM32 device, ADC1 channel 4 is mapped on GPIO pin PA.04 */
/* Enable GPIO Clock */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
/* Configure GPIO in analog mode to be used as ADC input */
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);
/*## Configuration of ADC ##################################################*/
/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
/* Enable ADC clock (core clock) */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC clock (conversion clock) common to several ADC instances */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_CLOCK_SYNC_PCLK_DIV2);
/* Set ADC measurement path to internal channels */
// LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_NONE);
/*## Configuration of ADC hierarchical scope: multimode ####################*/
/* Set ADC multimode configuration */
LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TRIPLE_REG_INTERL);
/* Set ADC multimode DMA transfer */
LL_ADC_SetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_REG_DMA_UNLMT_3);
/* Set ADC multimode: delay between 2 sampling phases */
/* Note: Delay has been chosen to have ADC2 conversion start in the
mid-delay between ADC1 conversions.
LL_ADC_SetMultiTwoSamplingDelay(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES);
/*## Configuration of ADC hierarchical scope: ADC instance #################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC data resolution */
// LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B);
/* Set ADC conversion data alignment */
// LL_ADC_SetResolution(ADC1, LL_ADC_DATA_ALIGN_RIGHT);
/* Set Set ADC sequencers scan mode, for all ADC groups
/* (group regular, group injected).
// LL_ADC_SetSequencersScanMode(ADC1, LL_ADC_SEQ_SCAN_DISABLE);
/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Set ADC group regular trigger source */
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group regular trigger polarity */
// LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);
/* Set ADC group regular continuous mode */
LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_CONTINUOUS);
/* Set ADC group regular conversion data transfer */
/* Note: Both ADC master and ADC slave have multimode setting
to use 1 DMA channel for all ADC instances.
In this case, each ADC instance must have setting of
ADC DMA request set to default value (no DMA transfer).
and ADC DMA transfer is managed by ADC common instance.
Refer to function "LL_ADC_SetMultiDMATransfer()".
LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
/* Set ADC group regular sequencer */
/* Note: On this STM32 serie, ADC group regular sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_REG_SetSequencerLength()".
/* Set ADC group regular sequencer length and scan direction */
LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);
/* Set ADC group regular sequencer discontinuous mode */
// LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
/* Set ADC group regular sequence: channel on the selected sequence rank. */
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC group injected trigger source */
// LL_ADC_INJ_SetTriggerSource(ADC1, LL_ADC_INJ_TRIG_SOFTWARE);
/* Set ADC group injected trigger polarity */
// LL_ADC_INJ_SetTriggerEdge(ADC1, LL_ADC_INJ_TRIG_EXT_RISING);
/* Set ADC group injected conversion trigger
// LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
/* Set ADC group injected sequencer */
/* Note: On this STM32 serie, ADC group injected sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_INJ_SetSequencerLength()".
/* Set ADC group injected sequencer length and scan direction */
// LL_ADC_INJ_SetSequencerLength(ADC1, LL_ADC_INJ_SEQ_SCAN_DISABLE);
/* Set ADC group injected sequencer discontinuous mode */
// LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
/* Set ADC group injected sequence: channel on the selected sequence rank. */
// LL_ADC_INJ_SetSequencerRanks(ADC1, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: channels #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Set ADC channels sampling time */
/* Note: Considering interruption occurring after each number of
"ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions
(IT from DMA transfer complete),
select sampling time and ADC clock with sufficient
duration to not create an overhead situation in IRQHandler.
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_0, LL_ADC_SAMPLINGTIME_3CYCLES);
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
/* Note: On this STM32 serie, there is only 1 analog watchdog available.
/* Set ADC analog watchdog: channels to be monitored */
// LL_ADC_SetAnalogWDMonitChannels(ADC1, LL_ADC_AWD_DISABLE);
/* Set ADC analog watchdog: thresholds */
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
// LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
/*## Configuration of ADC transversal scope: oversampling ##################*/
/* Note: Feature not available on this STM32 serie */
/* Note: in this example, ADC group regular end of conversions
(number of ADC conversions defined by DMA buffer size)
are notified by DMA transfer interruptions).
For multimode, configure ADC slave (ADC instance: ADC2)
and GPIO used by ADC channels.
Configuration of GPIO:
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
Configuration of ADC:
- Common to several ADC:
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
- Multimode
Not configured: same as ADC master (ADC slave shares the common configuration of ADC master)
In case re-use of this function outside of this example:
This function includes checks of ADC hardware constraints before
executing some configuration functions.
- In this example, all these checks are not necessary but are
implemented anyway to show the best practice usages
corresponding to reference manual procedure.
(On some STM32 series, setting of ADC features are not
conditioned to ADC state. However, in order to be compliant with
other STM32 series and to show the best practice usages,
ADC state is checked anyway with same constraints).
Software can be optimized by removing some of these checks,
if they are not relevant considering previous settings and actions
in user application.
- If ADC is not in the appropriate state to modify some parameters,
the setting of these parameters is bypassed without error
reporting:
it can be the expected behavior in case of recall of this
function to update only a few parameters (which update fullfills
the ADC state).
Otherwise, it is up to the user to set the appropriate error
reporting in user application.
Peripheral configuration is minimal configuration from reset values.
Thus, some useless LL unitary functions calls below are provided as
commented examples - setting is default configuration from reset.
* @retval None
void Configure_ADC_slave(void)
/*## Configuration of GPIO used by ADC channels ############################*/
/* Note: not configured: In this example, ADC slave group regular converts
the same channel as ADC master group regular.
Channel configuration same as ADC master.
/*## Configuration of ADC ##################################################*/
/* Enable ADC clock (core clock) */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC2);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC3);
/*## Configuration of ADC hierarchical scope: common to several ADC ########*/
/* Note: ADC clock (core clock) not configured: same as ADC master
(ADC slave shares the common clock of ADC master).
/* Note: not configured: same as ADC master (ADC slave shares the common
configuration of ADC master).
/*## Configuration of ADC hierarchical scope: multimode ####################*/
/* Note: not configured: same as ADC master (ADC slave shares the common
configuration of ADC master).
/*## Configuration of ADC hierarchical scope: ADC instance #################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC data resolution */
// LL_ADC_SetResolution(ADC2, LL_ADC_RESOLUTION_12B);
/* Set ADC conversion data alignment */
// LL_ADC_SetResolution(ADC2, LL_ADC_DATA_ALIGN_RIGHT);
/* Set Set ADC sequencers scan mode, for all ADC groups
/* (group regular, group injected).
LL_ADC_SetSequencersScanMode(ADC2, LL_ADC_SEQ_SCAN_ENABLE);
LL_ADC_SetSequencersScanMode(ADC3, LL_ADC_SEQ_SCAN_ENABLE);
/*## Configuration of ADC hierarchical scope: ADC group regular ############*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Set ADC group regular trigger source */
/* Note: On this STM32 device, in multimode, ADC slave trigger source
setting is mandatory: SW start.
LL_ADC_REG_SetTriggerSource(ADC2, LL_ADC_REG_TRIG_SOFTWARE);
LL_ADC_REG_SetTriggerSource(ADC3, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group regular continuous mode */
/* Note: On this STM32 device, in multimode, ADC slave continuous
conversions mode must be the same as ADC master.
LL_ADC_REG_SetContinuousMode(ADC2, LL_ADC_REG_CONV_CONTINUOUS);
LL_ADC_REG_SetContinuousMode(ADC3, LL_ADC_REG_CONV_CONTINUOUS);
/* Set ADC group regular conversion data transfer */
/* Note: Both ADC master and ADC slave have multimode setting
to use 1 DMA channel for all ADC instances.
In this case, each ADC instance must have setting of
ADC DMA request set to default value (no DMA transfer).
and ADC DMA transfer is managed by ADC common instance.
Refer to function "LL_ADC_SetMultiDMATransfer()".
LL_ADC_REG_SetDMATransfer(ADC2, LL_ADC_REG_DMA_TRANSFER_NONE);
LL_ADC_REG_SetDMATransfer(ADC3, LL_ADC_REG_DMA_TRANSFER_NONE);
/* Specify which ADC flag between EOC (end of unitary conversion)
/* or EOS (end of sequence conversions) is used to indicate
/* the end of conversion.
// LL_ADC_REG_SetFlagEndOfConversion(ADC2, LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV);
/* Set ADC group regular sequencer */
/* Note: On this STM32 serie, ADC group regular sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_REG_SetSequencerLength()".
/* Set ADC group regular sequencer length and scan direction */
LL_ADC_REG_SetSequencerLength(ADC2, LL_ADC_REG_SEQ_SCAN_DISABLE);
LL_ADC_REG_SetSequencerLength(ADC3, LL_ADC_REG_SEQ_SCAN_DISABLE);
/* Set ADC group regular sequencer discontinuous mode */
// LL_ADC_REG_SetSequencerDiscont(ADC2, LL_ADC_REG_SEQ_DISCONT_DISABLE);
/* Set ADC group regular sequence: channel on the selected sequence rank. */
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
LL_ADC_REG_SetSequencerRanks(ADC3, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, ADC state is checked anyway with standard requirements
(refer to description of this function).
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Note: Call of the functions below are commented because they are
useless in this example:
setting corresponding to default configuration from reset state. */
/* Set ADC group injected trigger source */
// LL_ADC_INJ_SetTriggerSource(ADC2, LL_ADC_INJ_TRIG_SOFTWARE);
/* Set ADC group injected trigger polarity */
// LL_ADC_INJ_SetTriggerEdge(ADC2, LL_ADC_INJ_TRIG_EXT_RISING);
/* Set ADC group injected conversion trigger
// LL_ADC_INJ_SetTrigAuto(ADC2, LL_ADC_INJ_TRIG_INDEPENDENT);
/* Set ADC group injected sequencer */
/* Note: On this STM32 serie, ADC group injected sequencer is
fully configurable: sequencer length and each rank
affectation to a channel are configurable.
Refer to description of function
"LL_ADC_INJ_SetSequencerLength()".
/* Set ADC group injected sequencer length and scan direction */
// LL_ADC_INJ_SetSequencerLength(ADC2, LL_ADC_INJ_SEQ_SCAN_DISABLE);
/* Set ADC group injected sequencer discontinuous mode */
// LL_ADC_INJ_SetSequencerDiscont(ADC2, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
/* Set ADC group injected sequence: channel on the selected sequence rank. */
// LL_ADC_INJ_SetSequencerRanks(ADC2, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_0);
/*## Configuration of ADC hierarchical scope: channels #####################*/
/* Note: not configured: In this example, ADC slave group regular converts
the same channel as ADC master group regular.
Channel configuration same as ADC master.
/*## Configuration of ADC transversal scope: analog watchdog ###############*/
/* Note: On this STM32 serie, there is only 1 analog watchdog available.
/* Set ADC analog watchdog: channels to be monitored */
// LL_ADC_SetAnalogWDMonitChannels(ADC2, LL_ADC_AWD_DISABLE);
/* Set ADC analog watchdog: thresholds */
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_HIGH, __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B));
// LL_ADC_SetAnalogWDThresholds(ADC2, LL_ADC_AWD_THRESHOLD_LOW, 0x000);
/*## Configuration of ADC transversal scope: oversampling ##################*/
/* Note: Feature not available on this STM32 serie */
/* Note: in this example, ADC group regular end of conversions
(number of ADC conversions defined by DMA buffer size)
are notified by DMA transfer interruptions).
Perform ADC activation procedure to make it ready to convert
(ADC instance: ADC1).
Operations:
- ADC instance
- Enable ADC
- ADC group regular
none: ADC conversion start-stop to be performed
after this function
- ADC group injected
none: ADC conversion start-stop to be performed
after this function
* @retval None
void Activate_ADC(void)
#if (USE_TIMEOUT == 1)
uint32_t Timeout = 0; /* Variable used for timeout management */
#endif /* USE_TIMEOUT */
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC1) == 0)
/* Enable ADC */
LL_ADC_Enable(ADC1);
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
/* Note: No operation on ADC group regular performed here.
ADC group regular conversions to be performed after this function
using function:
"LL_ADC_REG_StartConversion();"
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
/* Note: No operation on ADC group injected performed here.
ADC group injected conversions to be performed after this function */
using function:
"LL_ADC_INJ_StartConversion();"
Perform ADC activation procedure to make it ready to convert
(ADC instance: ADC2, used as ADC slave in multimode configuration).
Operations:
- ADC instance
- Enable ADC
- ADC group regular
none: ADC conversion start-stop to be performed
after this function
- ADC group injected
none: ADC conversion start-stop to be performed
after this function
* @retval None
void Activate_ADC_slave(void)
#if (USE_TIMEOUT == 1)
uint32_t Timeout = 0; /* Variable used for timeout management */
#endif /* USE_TIMEOUT */
/*## Operation on ADC hierarchical scope: ADC instance #####################*/
/* Note: Hardware constraint (refer to description of the functions
On this STM32 serie, setting of these features are not
conditioned to ADC state.
However, in order to be compliant with other STM32 series
and to show the best practice usages, ADC state is checked.
Software can be optimized by removing some of these checks, if
they are not relevant considering previous settings and actions
in user application.
if (LL_ADC_IsEnabled(ADC2) == 0)
/* Enable ADC */
LL_ADC_Enable(ADC2);
LL_ADC_Enable(ADC3);
/*## Operation on ADC hierarchical scope: ADC group regular ################*/
/* Note: No operation on ADC group regular performed here.
In ADC multimode group regular interleaved, ADC slave conversions
start and stop are controlled by ADC master.
/*## Operation on ADC hierarchical scope: ADC group injected ###############*/
/* Note: No operation on ADC group injected performed here.
ADC group injected conversions to be performed after this function */
using function:
"LL_ADC_INJ_StartConversion();"
System Clock Configuration
The system Clock is configured as follow :
System Clock source
= PLL (HSE)
SYSCLK(Hz)
AHB Prescaler
APB1 Prescaler
APB2 Prescaler
HSI Frequency(Hz)
Main regulator output voltage
= Scale1 mode
Flash Latency(WS)
* @retval None
void SystemClock_Config(void)
/* Enable HSE clock */
LL_RCC_HSE_EnableBypass();
LL_RCC_HSE_Enable();
while(LL_RCC_HSE_IsReady() != 1)
/* Set FLASH latency */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_7);
/* Enable PWR clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
/* Activation OverDrive Mode */
LL_PWR_EnableOverDriveMode();
while(LL_PWR_IsActiveFlag_OD() != 1)
/* Activation OverDrive Switching */
LL_PWR_EnableOverDriveSwitching();
while(LL_PWR_IsActiveFlag_ODSW() != 1)
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_8, 432, LL_RCC_PLLP_DIV_2);
LL_RCC_PLL_Enable();
while(LL_RCC_PLL_IsReady() != 1)
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
/* Set APB1 & APB2 prescaler */
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
/* Set systick to 1ms */
SysTick_Config( / 1000);
/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
SystemCoreClock = ;
CPU L1-Cache enable.
* @retval None
static void CPU_CACHE_Enable(void)
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
/******************************************************************************/
USER IRQ HANDLER TREATMENT
/******************************************************************************/
DMA transfer complete callback
This function is executed when the transfer complete interrupt
is generated
* @retval None
void AdcDmaTransferComplete_Callback()
uint32_t tmp_index = 0;
/* For the purpose of this example, dispatch multimode dual conversion data */
/* into arrays corresponding to ADC master and ADC slave conversion data.
/* Note: In a real application, this processing is useless and can be
avoided by setting multimode DMA transfer to one DMA channel
for each of ADC master and ADC slave.
Refer to function "LL_ADC_SetMultiDMATransfer()".
/* Management of the 2nd half of the buffer */
for (tmp_index = (ADC_CONVERTED_DATA_BUFFER_SIZE / 3); tmp_index & ADC_CONVERTED_DATA_BUFFER_SIZE; tmp_index++)
aADCxMultimodeDualMasterConvertedData[tmp_index] = (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_MASTER, aADCxADCyMultimodeDualConvertedData[tmp_index]);
aADCyMultimodeDualSlaveConvertedData[tmp_index]
= (uint16_t) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(LL_ADC_MULTI_SLAVE, aADCxADCyMultimodeDualConvertedData[tmp_index]);
/* Update status variable of DMA transfer */
ubDmaTransferStatus = 1;
USE_FULL_ASSERT
Reports the name of the source file and the source line number
where the assert_param error has occurred.
file: pointer to the source file name
line: assert_param error line source number
* @retval None
void assert_failed(uint8_t *file, uint32_t line)
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d", file, line) */
/* Infinite loop */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**&&******************************************************************************&&* @file&&&&Examples_LL/ADC/ADC_MultimodeDualInterleaved/Src/main.c&&* @author&&MCD Application Team&&* @version V1.0.0&&* @date&&&&30-December-2016&&* @brief&& This example describes how to use several ADC peripherals in&&*&&&&&&&&&&multimode, mode interleaved.&&*&&&&&&&&&&ADC master instance synchronizes and manages ADC slave instance.&&*&&&&&&&&&&Multimode interleaved combines ADC instances to convert&&*&&&&&&&&&&the same channel and increase the overall ADC conversion rate.&&*&&&&&&&&&&This example configures the ADC to perform conversions at the&&*&&&&&&&&&&maximum ADC conversion rate possible (with a sampling time&&*&&&&&&&&&&corresponding to ADC resolution 12 bits).&&*&&&&&&&&&&This example is based on the STM32F7xx ADC LL API;&&*&&&&&&&&&&Peripheral initialization done using LL unitary services functions.&&******************************************************************************&&* @attention&&*&&* &h2&&center&(C) COPYRIGHT(c) 2016 STMicroelectronics&/center&&/h2&&&*&&* Redistribution and use in source and binary forms, with or without modification,&&* are permitted provided that the following conditions are met:&&*&& 1. Redistributions of source code must retain the above copyright notice,&&*&&&&&&this list of conditions and the following disclaimer.&&*&& 2. Redistributions in binary form must reproduce the above copyright notice,&&*&&&&&&this list of conditions and the following disclaimer in the documentation&&*&&&&&&and/or other materials provided with the distribution.&&*&& 3. Neither the name of STMicroelectronics nor the names of its contributors&&*&&&&&&may be used to endorse or promote products derived from this software&&*&&&&&&without specific prior written permission.&&*&&* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"&&* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE&&* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE&&* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE&&* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL&&* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR&&* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER&&* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,&&* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE&&* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.&&*&&******************************************************************************&&*//* Includes ------------------------------------------------------------------*/#include "main.h"/** @addtogroup STM32F7xx_LL_Examples&&* @{&&*//** @addtogroup ADC_MultimodeDualInterleaved&&* @{&&*//* Private typedef -----------------------------------------------------------*//* Private define ------------------------------------------------------------*//* Definitions of ADC hardware constraints delays *//* Note: Only ADC IP HW delays are defined in ADC LL driver driver,&&&&&&&&&& *//*&&&&&& not timeout values:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&&&&& Timeout values for ADC operations are dependent to device clock&&&&&&*//*&&&&&& configuration (system clock versus ADC clock),&&&&&&&&&&&&&&&&&&&&&& *//*&&&&&& and therefore must be defined in user application.&&&&&&&&&&&&&&&&&& *//*&&&&&& Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout&&&& *//*&&&&&& values definition.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//* Timeout values for ADC operations. *//* (enable settling time, disable settling time, ...)&&&&&&&&&&&&&&&&&&&&&& *//* Values defined to be higher than worst cases: low clock frequency,&&&&&& *//* maximum prescalers.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//* Example of profile very low frequency : ADC clock frequency 36MHz&&&&&&&&*//* prescaler 2, sampling time 56 ADC clock cycles, resolution 12 bits.&&&&&&*//*&&- ADC enable time: maximum delay is 3 us&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&&&(refer to device datasheet, parameter "tSTAB")&&&&&&&&&&&&&&&&&&&&&&&&*//*&&- ADC disable time: maximum delay should be a few ADC clock cycles&&&&&&*//*&&- ADC stop conversion time: maximum delay should be a few ADC clock&&&& *//*&&&&cycles&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&- ADC conversion time: with this hypothesis of clock settings, maximum&&*//*&&&&delay will be 99us.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//*&&&&(refer to device reference manual, section "Timing")&&&&&&&&&&&&&&&&&&*//* Unit: ms&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */#define ADC_CALIBRATION_TIMEOUT_MS&&&&&& ((uint32_t)&& 1)#define ADC_ENABLE_TIMEOUT_MS&&&&&&&&&&&&((uint32_t)&& 1)#define ADC_DISABLE_TIMEOUT_MS&&&&&&&&&& ((uint32_t)&& 1)#define ADC_STOP_CONVERSION_TIMEOUT_MS&& ((uint32_t)&& 1)#define ADC_CONVERSION_TIMEOUT_MS&&&&&&&&((uint32_t)&& 2)/* Definitions of environment analog values *//* Value of analog reference voltage (Vref+), connected to analog voltage&& *//* supply Vdda (unit: mV).&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/#define VDDA_APPLI&&&&&&&&&&&&&&&&&&&&&& ((uint32_t)3300)/* Definitions of data related to this example *//* Init variable out of expected ADC conversion data range */#define VAR_CONVERTED_DATA_INIT_VALUE&&&&(__LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B) + 1)/* Definition of ADCx conversions data table size *//* Note: Considering interruption occurring after each number of&&&&&&&&&&&&*//*&&&&&& "ADC_CONVERTED_DATA_BUFFER_SIZE" ADC conversions&&&&&&&&&&&&&&&&&& *//*&&&&&& (IT from DMA transfer complete),&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& *//*&&&&&& select sampling time and ADC clock with sufficient&&&&&&&&&&&&&&&& *//*&&&&&& duration to not create an overhead situation in IRQHandler.&&&&&&&&*/#define ADC_CONVERTED_DATA_BUFFER_SIZE&& ((uint32_t) 256)/* Private macro -------------------------------------------------------------*//* Private variables ---------------------------------------------------------*//* Variables for ADC conversion data */__IO&& uint32_t aADCxADCyMultimodeDualConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];&&&& /* ADC multimode dual conversion data: ADC master and ADC slave conversion data are concatenated in a registers of 32 bits. */static uint16_t aADCxMultimodeDualMasterConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE];/* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC master conversion data. */static uint16_t aADCyMultimodeDualSlaveConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* For the purpose of this example, dispatch multimode dual conversion data into array corresponding to ADC slave conversion data. *//* Variable to report status of DMA transfer of ADC group regular conversions *//*&&0: DMA transfer is not completed&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&1: DMA transfer is completed&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*//*&&2: DMA transfer has not been started yet (initial state)&&&&&&&&&&&&&&&&&&*/__IO uint8_t ubDmaTransferStatus = 2; /* Variable set into DMA interruption callback *//* Private function prototypes -----------------------------------------------*/void&&&& SystemClock_Config(void);void&&&& Configure_DMA(void);void&&&& Configure_ADC(void);void&&&& Configure_ADC_slave(void);void&&&& Activate_ADC(void);void&&&& Activate_ADC_slave(void);static void CPU_CACHE_Enable(void);/* Private functions ---------------------------------------------------------*//**&&* @brief&&Main program&&* @param&&None&&* @retval None&&*/int main(void){&&&&/* Enable the CPU Cache */&&&&CPU_CACHE_Enable();&&&&/* Configure the system clock to 216 MHz */&&&&SystemClock_Config();&&&&/* Initialize button in EXTI mode */&&&&/* UserButton_Init(); */&&&&/* Configure DMA for data transfer from ADC */&&&&Configure_DMA();&&&&/* Configure ADC */&&&&/* Note: This function configures the ADC but does not enable it.&&&&&&&&&& */&&&&/*&&&&&& To enable it, use function "Activate_ADC()".&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&& This is intended to optimize power consumption:&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& 1. ADC configuration can be done once at the beginning&&&&&&&&&&&& */&&&&/*&&&&&&&&&&(ADC disabled, minimal power consumption)&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&& 2. ADC enable (higher power consumption) can be done just before&& */&&&&/*&&&&&&&&&&ADC conversions needed.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&&&&&&&Then, possible to perform successive "Activate_ADC()",&&&&&&&&&&*/&&&&/*&&&&&&&&&&"Deactivate_ADC()", ..., without having to set again&&&&&&&&&&&&*/&&&&/*&&&&&&&&&&ADC configuration.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&Configure_ADC();&&&&/* For multimode, configure ADC slave */&&&&Configure_ADC_slave();&&&&/* Activate ADC */&&&&/* Perform ADC activation procedure to make it ready to convert. */&&&&Activate_ADC();&&&&Activate_ADC_slave();&&&&LL_ADC_REG_StartConversionSWStart(ADC1);&&&&/* Infinite loop */&&&&while (1)&&&&{&&&&&&&&/* Note: ADC group regular conversion start is done into push button&&&&&&*/&&&&&&&&/*&&&&&& IRQ handler, refer to function "UserButton_Callback()".&&&&&&&&&&*/&&&&&&&&/* Note: LED state depending on DMA transfer status is set into DMA&&&&&& */&&&&&&&&/*&&&&&& IRQ handler, refer to functions "DmaTransferComplete()"&&&&&&&&&&*/&&&&&&&&/*&&&&&& and "DmaTransferHalfComplete()".&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/* Note: ADC conversion data are stored into array&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& "aADCxADCyMultimodeDualConvertedData".&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& For this example purpose, ADC conversion data of ADC master and&&*/&&&&&&&&/*&&&&&& ADC slave are dispatched into arrays */&&&&&&&&/*&&&&&& "aADCxMultimodeDualMasterConvertedData"&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& and "aADCyMultimodeDualSlaveConvertedData", refer to comments&&&&*/&&&&&&&&/*&&&&&& into function "DmaTransferComplete()".&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& (for debug: see variable content into watch window).&&&&&&&&&&&& */&&&&&&&&/* Note: ADC conversion data can be computed to physical values&&&&&&&&&& */&&&&&&&&/*&&&&&& using ADC LL driver helper macro:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&& uhADCxConvertedData_Voltage_mVolt&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&& = __LL_ADC_CALC_DATA_TO_VOLTAGE(VDDA_APPLI,&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&uhADCxConvertedData),&&&&&&&&&&&& */&&&&&&&&/*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&LL_ADC_RESOLUTION_12B)&&&&&&&&&&&&*/&&&&}}/**&&* @brief&&This function configures DMA for transfer of data from ADC&&* @param&&None&&* @retval None&&*/void Configure_DMA(void){&&&&/*## Configuration of NVIC #################################################*/&&&&/* Configure NVIC to enable DMA interruptions */&&&&NVIC_SetPriority(DMA2_Stream0_IRQn, 1);&&/* DMA IRQ lower priority than ADC IRQ */&&&&NVIC_EnableIRQ(DMA2_Stream0_IRQn);&&&&/*## Configuration of DMA ##################################################*/&&&&/* Enable the peripheral clock of DMA */&&&&LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);&&&&/* Configure the DMA transfer */&&&&/*&&- DMA transfer in circular mode to match with ADC configuration:&&&&&&&&*/&&&&/*&&&&DMA unlimited requests.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&/*&&- DMA transfer from ADC without address increment.&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer to memory with address increment.&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer from ADC by word to match with ADC configuration:&&&&&&&&*/&&&&/*&&&&ADC resolution 12 bits and and multimode enabled,&&&&&&&&&&&&&&&&&&&& */&&&&/*&&&&ADC master and ADC slave conversion data are concatenated in&&&&&&&&&&*/&&&&/*&&&&a register of 32 bits.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&- DMA transfer to memory by word to match with ADC conversion data&&&&&&*/&&&&/*&&&&buffer variable type: word.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_0, LL_DMA_CHANNEL_0);&&&&LL_DMA_ConfigTransfer(DMA2,&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_DIRECTION_PERIPH_TO_MEMORY |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MODE_CIRCULAR&&&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PERIPH_NOINCREMENT&&&&&&&& |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MEMORY_INCREMENT&&&&&&&&&& |&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PDATAALIGN_WORD&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_MDATAALIGN_WORD&&&&&&&&&&&&|&&&&&&&&&&&&&&&&&&&&&&&&&&LL_DMA_PRIORITY_HIGH&&&&&&&&&&&&&& );&&&&/* Set DMA transfer addresses of source and destination */&&&&/* Note: On this STM32 device, in multimode, ADC conversion data with&&&&&& */&&&&/*&&&&&& ADC master and ADC slave conversion data concatenated are located&&*/&&&&/*&&&&&& in a specific multimode data register.&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&LL_DMA_ConfigAddresses(DMA2,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA_MULTI),&&&&&&&&&&&&&&&&&&&&&&&&&& (uint32_t)&aADCxADCyMultimodeDualConvertedData,&&&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_DIRECTION_PERIPH_TO_MEMORY);&&&&/* Set DMA transfer size */&&&&LL_DMA_SetDataLength(DMA2,&&&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0,&&&&&&&&&&&&&&&&&&&&&&&& ADC_CONVERTED_DATA_BUFFER_SIZE);&&&&/* Enable DMA transfer interruption: transfer complete */&&&&LL_DMA_EnableIT_TC(DMA2,&&&&&&&&&&&&&&&&&&&&&& LL_DMA_STREAM_0);&&&&/*## Activation of DMA #####################################################*/&&&&/* Enable the DMA transfer */&&&&LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_0);}/**&&* @brief&&Configure ADC (ADC instance: ADC1) and GPIO used by ADC channels.&&* @note&& In case re-use of this function outside of this example:&&*&&&&&&&& This function includes checks of ADC hardware constraints before&&*&&&&&&&& executing some configuration functions.&&*&&&&&&&& - In this example, all these checks are not necessary but are&&*&&&&&&&&&& implemented anyway to show the best practice usages&&*&&&&&&&&&& corresponding to reference manual procedure.&&*&&&&&&&&&& (On some STM32 series, setting of ADC features are not&&*&&&&&&&&&& conditioned to ADC state. However, in order to be compliant with&&*&&&&&&&&&& other STM32 series and to show the best practice usages,&&*&&&&&&&&&& ADC state is checked anyway with same constraints).&&*&&&&&&&&&& Software can be optimized by removing some of these checks,&&*&&&&&&&&&& if they are not relevant considering previous settings and actions&&*&&&&&&&&&& in user application.&&*&&&&&&&& - If ADC is not in the appropriate state to modify some parameters,&&*&&&&&&&&&& the setting of these parameters is bypassed without error&&*&&&&&&&&&& reporting:&&*&&&&&&&&&& it can be the expected behavior in case of recall of this&&*&&&&&&&&&& function to update only a few parameters (which update fullfills&&*&&&&&&&&&& the ADC state).&&*&&&&&&&&&& Otherwise, it is up to the user to set the appropriate error&&*&&&&&&&&&& reporting in user application.&&* @note&& Peripheral configuration is minimal configuration from reset values.&&*&&&&&&&& Thus, some useless LL unitary functions calls below are provided as&&*&&&&&&&& commented examples - setting is default configuration from reset.&&* @param&&None&&* @retval None&&*/void Configure_ADC(void){&&&&/*## Configuration of GPIO used by ADC channels ############################*/&&&&/* Note: On this STM32 device, ADC1 channel 4 is mapped on GPIO pin PA.04 */&&&&/* Enable GPIO Clock */&&&&LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);&&&&/* Configure GPIO in analog mode to be used as ADC input */&&&&LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);&&&&/*## Configuration of ADC ##################################################*/&&&&/*## Configuration of ADC hierarchical scope: common to several ADC ########*/&&&&/* Enable ADC clock (core clock) */&&&&LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);&&&&/* Note: Hardware constraint (refer to description of the functions&&&&&&&& */&&&&/*&&&&&& below):&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& On this STM32 serie, setting of these features are not&&&&&&&&&&&& */&&&&/*&&&&&& conditioned to ADC state.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& However, in order to be compliant with other STM32 series&&&&&&&&&&*/&&&&/*&&&&&& and to show the best practice usages, ADC state is checked.&&&&&&&&*/&&&&/*&&&&&& Software can be optimized by removing some of these checks, if&&&& */&&&&/*&&&&&& they are not relevant considering previous settings and actions&&&&*/&&&&/*&&&&&& in user application.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE() == 0)&&&&{&&&&&&&&/* Note: Call of the functions below are commented because they are&&&&&& */&&&&&&&&/*&&&&&& useless in this example:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& setting corresponding to default configuration from reset state. */&&&&&&&&/* Set ADC clock (conversion clock) common to several ADC instances */&&&&&&&&LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_CLOCK_SYNC_PCLK_DIV2);&&&&&&&&/* Set ADC measurement path to internal channels */&&&&&&&&// LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_NONE);&&&&&&&&/*## Configuration of ADC hierarchical scope: multimode ####################*/&&&&&&&&/* Set ADC multimode configuration */&&&&&&&&LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TRIPLE_REG_INTERL);&&&&&&&&/* Set ADC multimode DMA transfer */&&&&&&&&LL_ADC_SetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_REG_DMA_UNLMT_3);&&&&&&&&/* Set ADC multimode: delay between 2 sampling phases */&&&&&&&&/* Note: Delay has been chosen to have ADC2 conversion start in the&&&&&& */&&&&&&&&/*&&&&&& mid-delay between ADC1 conversions.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&LL_ADC_SetMultiTwoSamplingDelay(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES);&&&&}&&&&/*## Configuration of ADC hierarchical scope: ADC instance #################*/&&&&/* Note: Hardware constraint (refer to description of the functions&&&&&&&& */&&&&/*&&&&&& below):&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& On this STM32 serie, setting of these features are not&&&&&&&&&&&& */&&&&/*&&&&&& conditioned to ADC state.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& However, ADC state is checked anyway with standard requirements&&&&*/&&&&/*&&&&&& (refer to description of this function).&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&if (LL_ADC_IsEnabled(ADC1) == 0)&&&&{&&&&&&&&/* Note: Call of the functions below are commented because they are&&&&&& */&&&&&&&&/*&&&&&& useless in this example:&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& setting corresponding to default configuration from reset state. */&&&&&&&&/* Set ADC data resolution */&&&&&&&&// LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B);&&&&&&&&/* Set ADC conversion data alignment */&&&&&&&&// LL_ADC_SetResolution(ADC1, LL_ADC_DATA_ALIGN_RIGHT);&&&&&&&&/* Set Set ADC sequencers scan mode, for all ADC groups&&&&&&&&&&&&&&&&&& */&&&&&&&&/* (group regular, group injected).&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&// LL_ADC_SetSequencersScanMode(ADC1, LL_ADC_SEQ_SCAN_DISABLE);&&&&}&&&&/*## Configuration of ADC hierarchical scope: ADC group regular ############*/&&&&/* Note: Hardware constraint (refer to description of the functions&&&&&&&& */&&&&/*&&&&&& below):&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& On this STM32 serie, setting of these features are not&&&&&&&&&&&& */&&&&/*&&&&&& conditioned to ADC state.&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& However, ADC state is checked anyway with standard requirements&&&&*/&&&&/*&&&&&& (refer to description of this function).&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&if (LL_ADC_IsEnabled(ADC1) == 0)&&&&{&&&&&&&&/* Set ADC group regular trigger source */&&&&&&&&LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);&&&&&&&&/* Set ADC group regular trigger polarity */&&&&&&&&// LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);&&&&&&&&/* Set ADC group regular continuous mode */&&&&&&&&LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_CONTINUOUS);&&&&&&&&/* Set ADC group regular conversion data transfer */&&&&&&&&/* Note: Both ADC master and ADC slave have multimode setting&&&&&&&&&&&& */&&&&&&&&/*&&&&&& to use 1 DMA channel for all ADC instances.&&&&&&&&&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& In this case, each ADC instance must have setting of&&&&&&&&&&&& */&&&&&&&&/*&&&&&& ADC DMA request set to default value (no DMA transfer).&&&&&&&&&&*/&&&&&&&&/*&&&&&& and ADC DMA transfer is managed by ADC common instance.&&&&&&&&&&*/&&&&&&&&/*&&&&&& Refer to function "LL_ADC_SetMultiDMATransfer()".&&&&&&&&&&&&&&&&*/&&&&&&&&LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);&&&&&&&&/* Set ADC group regular sequencer */&&&&&&&&/* Note: On this STM32 serie, ADC group regular sequencer is&&&&&&&&&&&&&&*/&&&&&&&&/*&&&&&& fully configurable: sequencer length and each rank&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& affectation to a channel are configurable.&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& Refer to description of function&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/*&&&&&& "LL_ADC_REG_SetSequencerLength()".&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& */&&&&&&&&/* Set ADC group regular sequencer length and scan direction */&&&&&&&&LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);&&&&&&&&/* Set ADC group regular sequencer discontinuous mode */&&&&&&&&// LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);&&&&&&&&/* Set ADC group regular sequence: channel on the selected sequence rank. */&&&&&&&&LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);&&&&}&&&&/*## Configuration of ADC hierarchical scope: ADC group injected ###########*/&&&&/* Note: Hardware constraint (refer to description of the functions&&&&&&&& */&&&&/*&&&&&& below):&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/&&&&/*&&&&&& On this STM32 serie, setting of these features are not&&&&&&&&&&&& */&&&&/*&&&&&& conditioned to ADC state.&&&&&&&&&