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DDR3 Data Exchange Solution on Zynq7000
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实验中通过Zynq7000 PL采集ADC数据，处理后经PS HP0 -& DDR3 Controller 存储至DDR3，解决方案有两种：方案一：PL端采集ADC的数据直接经PS HP0 -& DDR3 Controller 存储至DDR3，但是测试的时候发现数据读写都有问题。为了验证此问题，做如下测试：首先确保PS读写通道工作正常，再通过PL写，PS读，读回来的数据不对，说明PL写操作可能有问题；最后通过PS写，PL读，读回来的数据也有问题（地址跟数据不对应），分析其原因可能是AXI 互连机制仲裁的问题。因为PL和PS同时访问DDR3，AXI总线上有两个Master，这就需要一个AXI仲裁器，但是PL端设计没有仲裁功能【参阅P034 DDR3数据交换解决方案】。 (PS端是否有仲裁机制，需进一步了解）。方案二：根据方案一遇到的问题，考虑在PL端加一个DMA，图示为在ZedBoard板上测试DDR3数据交换设计方案，经测试数据交换正确。如果总线生存在多个Master，就需要仲裁器来决定如何控制各种主模块对总线的访问，对Zynq而言，每个AXI互连机制是采用两级仲裁方案来解决访问冲突的。本编文章的目的主要用简明的方法对DDR3进行读写，当然这种方式每次读写都需要CPU干预，效率是比较低的，但是这是学习的过程吧。
本系列文章尽可能的让每一个实验都相对独立，过程尽可能保证完整性，保证实验的可重现性。 但是用到的模块或者IP的具体作用和用法不保证都重复详细的介绍。
本文所使用的开发板是兼容zedboardPC 开发环境版本：Vivado 2015.4 Xilinx SDK 2015.4
生成硬件系统
新建vivado工程
选择Zedboard
新建Block Design
添加ZYNQ PS
点击Run Block Automation,让vivado自动配置好zedboard相关的默认的信息，点击OK
双击ZYNQ，在此可以去掉一些不用的外设
设置好的Block Design如图所示
在block design上右击，选择Create HDL Wapper
完成后，在block design上右击，选择Generate Output Prouducts,在弹出的对话框选择Generate
点击Generate Bitstream
完成后，选择File-&Export-&Export Hadfware,选中Include bitsteam
File -& Launch SDK，把硬件架构导出到软件工程
编写软件程序
新建Hello工程
DDR3的地址
建好后，在mem_demo_bsp-&ps7-&cortexa9_0的路径下，打开xparameters_ps.h这个头文件，这个头文件是cortexA9可以直接控制的外设地址的宏定义。在里面可以找到DDR的地址，可以看到如下代码：&/* Canonical definitions for DDR MEMORY */&#define XPAR_DDR_MEM_BASEADDR 0xU&#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU&等会我们要使用这个地址，对DDR3进行读写操作
读写操作函数
在mem_demo_bsp-&ps7-&cortexa9_0的路径下，打开xil_io.h这个头文件，这个头文件是cortexA9可以直接控制的内存映射或者映射到了地址空间的IO。在里面可以看到如下代码：&//从某个地址读数据&u8 Xil_In8(INTPTR Addr);&u16 Xil_In16(INTPTR Addr);&u32 Xil_In32(INTPTR Addr);
//向某个地址写数据。&void Xil_Out8(INTPTR Addr, u8 Value);&void Xil_Out16(INTPTR Addr, u16 Value);&void Xil_Out32(INTPTR Addr, u32 Value);&OK,有了这些就可以简单的对DDR进行续写操作了
#include "stdio.h"
#include "platform.h"
#include "xparameters.h"
#include "xparameters_ps.h"#include "xil_printf.h"
#include "xil_io.h"
#define DDR_BASEARDDR
XPAR_DDR_MEM_BASEADDR + 0x
int main()
init_platform();
xil_printf("Hello World\n\r");
for(i=0; i&32; i++)
Xil_Out32(DDR_BASEARDDR+i*4,i);
for(i=0; i&32; i++)
rev = Xil_In32(DDR_BASEARDDR+i*4);
xil_printf("the address at
%x data is : %x \n\r" ,DDR_BASEARDDR+i*4, rev);
cleanup_platform();
串口终端的结果如下：&Hello World&the address at
data is : 0&the address at
data is : 1&the address at
data is : 2&the address at 1000000C data is : 3&the address at
data is : 4&the address at
data is : 5&the address at
data is : 6&the address at 1000001C data is : 7&the address at
data is : 8&the address at
data is : 9&the address at
data is : A&the address at 1000002C data is : B&the address at
data is : C&the address at
data is : D&the address at
data is : E&the address at 1000003C data is : F&the address at
data is : 10&the address at
data is : 11&the address at
data is : 12&the address at 1000004C data is : 13&the address at
data is : 14&the address at
data is : 15&the address at
data is : 16&the address at 1000005C data is : 17&the address at
data is : 18&the address at
data is : 19&the address at
data is : 1A&the address at 1000006C data is : 1B&the address at
data is : 1C&the address at
data is : 1D&the address at
data is : 1E&the address at 1000007C data is : 1F
阅读(...) 评论()设计技术&&
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& [原创] Xilinx Zybo Zynq－7000ARM－FPGA全编程SoC解决方案
[原创] Xilinx Zybo Zynq－7000ARM－FPGA全编程SoC解决方案
时间： 10:15:12&&&&&&
作者：Xilinx&&&&&&
来源：中电网
Xilinx公司的Zynq&-7000系列是基于Xilinx全编程的系统级芯片(SoC)架构,集成了功能丰富的双核或单核ARM& Cortex™-A9处理系统(PS)和28nm Xilinx.ARM& Cortex™-A9 CPU是处理系统的心脏,包括了片上存储器,外接存储器接口和各种外设连接接口.主要用在汽车辅助驾驭,驾驭信息和娱乐系统,广播照相机,工业马达控制,工业网络和机器视角,IP和智能照相机,LTE无线和基带,医疗诊断和成像,多功能打印机以及视频和夜视设备.本文介绍了Zynq-7000 FPGA主要特性和架构图,以及Zybo Zynq-7000 ARM/FPGA SoC培训板主要特性和优势,主要元件分布图与电路图.The Zynq&-7000 family is based on the Xilinx All Programmable SoC architecture. These products integrate a feature-rich dual-core or single-core ARM& Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.The Zynq-7000 family offers the flexibility and lability of an FPGA, while providing performance, power, and ease of usetypically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 family allows designers to targetcost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While eachdevice in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, theZynq-7000 and Zynq-7000S SoCs are able to serve a wide range of applications including:• Automotive driver assistance, driver information, and infotainment• Broadcast camera• Industrial motor control, industrial networking, and machine vision• IP and Smart camera• LTE radio and baseband• Medical diagnostics and imaging• Multifunction printers• Video and night vision equipmentThe Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS. It allows forthe realization of unique and differentiated system functions. The integration of the PS with the PL allows levels ofperformance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency,and power budgets.Xilinx offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux device drivers are available for theperipherals in the PS and the PL. The Vivado& Design Suite development environment enables a rapid productdevelopment for software, hardware, and systems engineers. Adoption of the ARM-based PS also brings a broad range ofthird-party tools and IP providers in combination with Xilinx’s existing PL ecosystem.The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operatingsystems used with the Cortex-A9 processor are also available for the Zynq-7000 family.The PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for powermanagement if required. The processors in the PS always boot first, allowing a software centric approach for PLconfiguration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.Zynq-7000 FPGA主要特性:Processing System (PS)ARM Cortex-A9 BasedApplication Processor Unit (APU)&# DMIPS/MHz per CPU• CPU : Up to 1 GHz• Coherent multiprocessor support• ARMv7-A architecture• TrustZone& security• Thumb&-2 instruction set• Jazelle& RCT execution Environment Architecture• NEON™ media-processing engine• Single and double precision Vector Floating Point Unit (VFPU)• CoreSight™ and Program Trace Macrocell (PTM)• Timer and Interrupts• Three watchdog timers• One global timer• Two triple-timer countersCaches• 32 KB Level 1 4-way set-associative instruction and data caches(independent for each CPU)&# KB 8-way set-associative Level 2 cache(shared between the CPUs)• Byte-parity supportOn-Chip Memory• On-chip boot ROM&# KB on-chip RAM (OCM)• Byte-parity supportExternal Memory Interfaces• Multiprotocol dynamic memory controller• 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2memories• ECC support in 16-bit mode• 1GB of address space using single rank of 8-, 16-, or 32-bit-widememories• Static memory interfaces• 8-bit SRAM data bus with up to 64 MB support• Parallel NOR flash support• ONFI1.0 NAND flash support (1-bit ECC)• 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit)serial NOR flash8-Channel DMA Controller• Memory-to-memory, memory-to-peripheral, peripheral-to-memory,and scatter-gather transaction supportI/O Peripherals and Interfaces• Two 10/100/1000 tri-speed Ethernet MAC peripherals withIEEE Std 802.3 and IEEE Std 1588 revision 2.0 support• Scatter-gather DMA capability• Renition of 1588 rev. 2 PTP frames• GMII, RGMII, and SGMII interfaces• Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints• USB 2.0 compliant device IP core• Supports on-the-go, high-speed, full-speed, and low-speedmodes• Intel EHCI compliant USB host• 8-bit ULPI external PHY interface• Two full CAN 2.0B compliant CAN bus interfaces• CAN 2.0-A and CAN 2.0-B and ISO
standardcompliant• External PHY interface• Two SD/SDIO 2.0/MMC3.31 compliant controllers• Two full-duplex SPI ports with three peripheral chip selects• Two high-speed UARTs (up to 1 Mb/s)• Two master and slave I2C interfaces• GPIO with four 32-bit banks, of which up to 54 bits can be used withthe PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits(up to two banks of 32b) connected to the Programmable Logic• Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignmentsInterconnect• High-bandwidth connectivity within PS and between PS and PL• ARM AMBA& AXI based• QoS support on critical masters for latency and bandwidth controlProgrammable Logic (PL)Configurable Logic Blocks (CLB)• Look-up tables (LUT)• Flip-flops• Cascadeable adders36 Kb Block RAM• True Dual-Port• Up to 72 bits wide• Configurable as dual 18 Kb block RAMDSP Blocks• 18 x 25 signed multiply• 48-bit adder/accumulator• 25-bit pre-adderProgrammable I/O Blocks• Supports LVCMOS, LVDS, and SSTL&#V to 3.3V I/O• Programmable I/O delay and SerDesJTAG Boundary-Scan• IEEE Std 1149.1 Compatible Test InterfacePCI Express& Block• Supports Root complex and End Point configurations• Supports up to Gen2 speeds• Supports up to 8 lanesSerial Transceivers• Up to 16 receivers and transmitters• Supports up to 12.5 Gb/s data ratesTwo 12-Bit Analog-to-Digital Converters• On-chip voltage and temperature sensing• Up to 17 external differential input channels• One million samples per second maximum conversion rate图1.Zynq-7000 FPGA架构图Zybo Zynq-7000 ARM/FPGA SoC培训板The Zybo (Zynq™ Board) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is based on the Xilinx& All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series field programmable gate array (FPGA) logic. When coupled with the rich set of multimedia and connectivity peripherals available on the Zybo, the Zynq Z-7010 can host a whole system design. The on-board memories, video and audio I/O, dual-role USB, Ethernet and SD slot will have your design up-and-ready with no additional hardware needed. Additionally, six Pmod connectors are available to put any design on an easy growth path. The Zybo provides an ultra-low cost alternative to the ZedBoard for designers that don’t require the high-density I/O of the FMC connector, but still wish to leverage the massive processing power and extensibility of the Zynq AP SoC architecture.Zybo Zynq-7000 ARM/FPGA SoC培训板主要特性和优势:128 Mb Serial Flash w/ QSPI interface16-bits per pixel VGA output port240 KB Block RAM28,000 logic cells512 MB x32 DDR3 w/ 1050Mbps bandwidth650 MHz dual-core Cortex™-A9 processor80 DSP slicesAudio codec with headphone out, microphone and line in jacksDDR3 memory controller with 8 DMA channelsDual-role (Source/Sink) HDMI portExternal EM (programmed with 48-bit globally unique EUI-48/64™ compatible identifier)GPIO: 6 pushbuttons, 4 slide switches, 5 LEDsHigh-bandwith peripheral controllers: 1G Ethernet, USB 2.0, SDIOLow-bandwidth peripheral controller: SPI, UART, I2COTG USB 2.0 PHY (supports host and device)On-board JTAG programming and UART to USB converterOn-chip dual channel, 12-bit, 1 MSPS analog-to-digital converter (XADC)Six Pmod ports (1 processor-dedicated, 1 dual analog/digital)Trimode (1Gbit/100Mbit/10Mbit) Ethernet PHYXilinx Zynq-7000 (XC7Z010-1CLG400C)microSD slot (supports Linux file system)图2.Zybo Zynq-7000 ARM/FPGA SoC培训板外形图Zybo Zynq-7000 ARM/FPGA SoC培训板数字元件对应表:图3.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(1)图4.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(2)图5.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(3)图6.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(4)图7.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(5)图8.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(6)图9.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(7)图10.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(8)图11.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(9)图12.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(10)图13.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(11)图14.Zybo Zynq-7000 ARM/FPGA SoC培训板电路图(12)详情请见:和以及
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[下一篇：]在Zynq上用MIG扩展内存(1)-XPS篇
来源：Xilinx
发布时间：[]
　　硬件平台：ZC706开发板
　　软件工具：XPS & SDK 14.4
　　MIG(Memory Interface Generator)的基本配置：
　　AXI接口: 200MHz, 32bit
　　Memory接口: 800MHz, 64bit
　　Step 1: 创建工程
　　启动XPS 14.4。用器件XC7Z045(FFG900, -2)创建一个新的工程。创建工程时不要选择&AXI Reset Module&。
　　Step 2: 配置Zynq
　　按照labfiles里面的Zynq-PS-DDR-Configuration.png配置PS DDR3的参数。
　　将CPU的频率设置为733MHz
　　取消&Enable Programmable Clock and reset to PL&
　　取消&Enable PL Interrupts to PS and vice versa&
　　取消所有外设，仅仅保留UART。UART1使用MIO 48..49
　　Step 3: 配置Clock Generator
　　CLKIN：Frequency=
　　CLKOUT0：Frequency=, Phase=337.5, Group=PLLE0, Buffered=FALSE
　　CLKOUT1：Frequency=, Phase=0, Group=PLLE0, Buffered=FALSE
　　CLKOUT2：Frequency=, Phase=10, Group=PLLE0, Buffered=FALSE
　　CLKOUT3：Frequency=, Phase=0, Group=PLLE0, Buffered=TRUE
　　CLKOUT4：Frequency=, Phase=0, Group=PLLE0, Buffered=TRUE
　　注意: CLKOUT2是为axi_7series_ddrx_0::sync_pulse提供时钟的，必须是CLKOUT0
(axi_7series_ddrx_0::freq_refclk)的1/16。
　　Step 4: 配置MIG
　　从IP Catalog 里面添加 &AXI 7 Series Memory Controller(DDR2/DDr3)& 到当前设计
　　配置PHY to Controller Clock Ratio为4:1
　　配置Memory Type=SODIMMS; Memory Part=MT8JTF12864HZ-1G6
　　更改AR/AW/B/R/W 寄存器的状态为&AUTOMATIC&
　　确认RTT为RZQ/4
　　选中&DCI Cascading&
　　从labfiles\zc706_ddr3_sodimm_pinout.ucf中导入DDR3的管脚配置
　　将axi_7series_ddrx_0的内存大小修改为1GB
　　在所有axi_7series_ddrx_0:: (IO_IF)memory_0端口(除了parity)上单击右键，选择Make
external。
　　Step 5: 建立IP之间的连接
　　axi_7series_ddrx_0::clk_ref &-& clock_generator_0::CLKOUT3
　　axi_7series_ddrx_0::mem_refclk &-& clock_generator_0::CLKOUT1
　　axi_7series_ddrx_0::freq_refclk &-& clock_generator_0::CLKOUT0
　　axi_7series_ddrx_0:: pll_lock &-& clock_generator_0::LOCKED
　　axi_7series_ddrx_0::sync_pulse &-& clock_generator_0::CLKOUT2
　　axi_7series_ddrx_0:: S_AXI::clk &-& clock_generator_0::CLKOUT4
　　processing_system7_0::M_AXI_GP0::M_AXI_GP0_ACLK &-&
clock_generator_0::CLKOUT4
　　axi_interconnect_1::INTERCONNECT_ACLK &-&
clock_generator_0::CLKOUT4
　　axi_interconnect_1::INTERCONNECT_aresetn &-&
clock_generator_0::LOCKED (Done in column Net)
　　在&clock_generator_0::RST &上单击右键，选择Make external。将External
Port下面的&clock_generator_0_RST_pin&名字更改为 &RESET&类匹配相应的ucf约束
　　Step 6：GUI之外的更改
　　关闭当前工程。
　　用文本编辑器打开system.mhs，找到CLKOUT2并添加DUTY_CYCLE
　　PARAMETER C_CLKOUT2_FREQ =
　　PARAMETER C_CLKOUT2_PHASE = 10
　　PARAMETER C_CLKOUT2_DUTY_CYCLE = 0.0625
　　PARAMETER C_CLKOUT2_GROUP = PLLE0
　　PARAMETER C_CLKOUT2_BUF = FALSE
　　用labfiles\ system.ucf替换&data&目录下的同名文件
　　Step 7：生成BitStream
　　重新打开工程，电机Generate BitStream生成.bit文件，然后Export Design to SDK。
　　在SDK里面，可以用模板&Memory Tests&创建一个工程，测试确认MIG工作正常。
　　Zynq PL侧的DDR PHY的最高速率为1866Mbps。如果配置MIG的&PHY to Controller Clock
Ratio&为4:1，MIG的AXI端口的最高工作频率只能到233.33MHz。如果PL里面的IP对MIG的访问数据量比较大，这种配置有优势。如果CPU通过MIG访问扩展内存比较频繁，就需要提高MIG的AXI端口的工作频率。
　　以下面的MIG配置为例:
　　AXI接口: 250MHz, 32bit
　　Memory接口: 500MHz, 64bit
　　在上面的基础上，要做以下修改：
　　Step 3: 配置Clock Generator:
　　CLKIN：Frequency=
　　CLKOUT0：Frequency=, Phase=337.5, Group=PLLE0, Buffered=FALSE
　　CLKOUT1：Frequency=, Phase=0, Group=PLLE0, Buffered=FALSE
　　CLKOUT2：Frequency=, Phase=10, Group=PLLE0, Buffered=FALSE
　　CLKOUT3：Frequency=, Phase=0, Group=PLLE0, Buffered=TRUE
　　CLKOUT4：Frequency=, Phase=0, Group=PLLE0, Buffered=TRUE
　　Step 4: 配置MIG
　　配置PHY to Controller Clock Ratio为2:1
　　在Ports Tab页面单击右键，使能Net列的显示。将axi_7series_ddrx_0::
(IO_IF)memory_0下所有的net的名字删除掉前缀&axi_7series_ddrx_0_&，然后将External
Ports下MIG对应的信号的名字也删除前缀。这可以帮助工具完成时序收敛。
　　在新的配置下，CPU通过MIG访问扩展DDR3内存的吞吐量会得到一定的提升。通过分析Timing
Analyzer发现，MIG的工作频率在250MHz的基础上还有小幅的提升空间。
　　==END==
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pcb上zynq ps ddr3 的地址线顺序全部弄反了有软件解决方法吗
发帖数： 4
我自己画了一块zynq的板子，上面用的是 xc7z020-clg484-2i，内存颗粒用的是mt41k256m16-ha125e，在原理图阶段不小心把ps上的addr全部逆序了，导致pcb焊接回来后调试时内存有问题。
现在我让裸程序运行在ps 的 ocm(on chip memory)上，通过代码读写dram，如果只读固定的几个位置，读写都是正确的，也不会跑飞，但是如果顺序的操作dram，比如用for循环给一片dram地址赋直，ps就会跑飞。再次用jtag调试需要给板子重新上电。
想问问大家，这个错误有软件解决方法吗，或者有没有什么别的任何建议
1. 错误的原理图
2. vivado的ps ddr3配置
3. 测试代码
4. 读写dram连续地址（20，1的地方就是ps跑飞了的位置）
5. 读写dram固定地址
条消息（共 2 条）
(5,248 查看）
发帖数： 4
忘了来回复了，后来的结果是没有处理方法，最后重新画pcb解决问题
条消息（共 2 条）
(857 查看）
发帖数： 4
忘了来回复了，后来的结果是没有处理方法，最后重新画pcb解决问题
条消息（共 2 条）
(858 查看）