ISE 综合面积报告分析_中华文本库
第1页/共4页
ISE 综合面积报告分析
.cn/s/blog_0ywmw.html
Ref: http://www.baisi.net/viewthread.php?tid=307745
【原创】如何知道你的FPGA 设计等效于多少门
FPGA 的最终面积不但和要实现的功能有关，而且和不同人的不同设计方法有关，比如同样一个buffer ，用block memory 和 coregen 的方法可能面积很省，但是如果直接用RTL 编码产生，而且不幸没有综合成blockmem 而是综合成了一大堆的寄存器和LUT 则面积会很大，大到不可想象 （我有个这样的经历）。所以要在设计前就估计出面积不太可行。除非公司开发的产品有很强的延续性，那样的话可以根据原来的项目进行近似的推算，这是可能 的。
那么在ISE 里面如何看到自己设计的部分的面积呢
1. 在ISE 项目中打开“view design summary”。
在右侧design summary窗口中选择“detailed reports”中的“map report”。
2. 出现如下所示的内容。我们分析一下。
Design Summary
Logic Utilization:
1. FPGA资源利用率
Number of Slice Flip Flops:
11,555 out of 178,176
6% Slice内部FF 寄存器利用率：6%.
Number of 4 input LUTs:
21,446 out of 178,176
12% 输入LUT 利用率：12%
Logic Distribution:
被使用的FPGA 资源分布情况
Number of occupied Slices:
16,079 out of
18% 占用的Slice 数目：18%
为什么Slice 利用率是18%而上面的LUT 利用率是12%呢？简单说明一下。假如一个Slice 有两个LUT ，片内总共有100个单位的Slice ， 也即有200个单位的LUT ，那么如果我们的设计使用了24个单元的LUT ，而这些LUT 分布在18个Slice 里面时，恰好就是现在的这种情况了。即 Slice 利用率18% （18/100），LUT 利用率12%（24/200）。
Number of Slices containing only related logic:
16,079 out of
100% Slice 里面只有互相相关的逻辑，这种Slice 所占比例：100%
Number of Slices containing unrelated logic:
第1页/共4页
寻找更多 ""ISE综合布线生成的最终报告(Design Summary)或者MAP Report中：
Logic Distribution:
& Number of occupied Slices:&&&&&&& 1,341 out of&& 9,280&& 14%
& Number of Slices containing only related logic:&& 1,341 out of&& 1,341& 100%
& Number of Slices containing unrelated logic:&&&&&&&&& 0 out of&& 1,341&&& 0%
&&&&&&& *See NOTES below for an explanation of the effects of unrelated logic
两种logic（related logic和unrelated logic）的区别和联系?
http://www.edacn.net/bbs/viewthread.php?tid=13808
Xilinx的Slice内部结构图，一般是1个LUT和1个DFF构成1个LC，这种结构符合FPGA设计的一般规律，也就是作一些组合逻辑然后触发器
打一拍。但是不是所有的设计都是这样的，可能是几个LUT后才会打一拍，所以为了提高器件资源的利用率，Xilinx在LUT和DFF之间设计了抽头，允
许独自分别使用LUT或DFF，也就是两个不相关的逻辑可以放在同一个SLICE中，分别占用SLICE的LUT和DFF资源。当然这样做的前提是器件内
部的SLICE资源已经完全占用。所以在报告中，所谓realted logic就是一个SLICE中只有相关逻辑；而unrelated
logic就是一个SLICE中放入了两部分无关逻辑。当SLICE占用率到了99％之后，就有可能出现unrelated
logic了，否则100％都是related
logic。所以说在看器件占用率的时候，不要只看Slice的占用率，要看LUT和DFF的占用率，即使SLICE占用率达到了99%，还是可以放入很
多逻辑的，这时unrelated logic的比例会增加，对于Xilinx的VII、VII
Pro器件来说，布线资源很丰富，所以即使占用资源很多也还是可以跑通的。这也是相比Altera的一个优势吧，我见过的设计unrelated
logic已经占用到50%了，还跑到83MHz，可以说是把器件用得很充分了。
&& Related logic is defined as being logic that shares connectivity - e.g. two
&& LUTs are &related& if they share common inputs.& When assembling slices,
&& Map gives priority to combine logic that is related.& Doing so results in
&& the best timing performance.
&& Unrelated logic shares no connectivity.& Map will only begin packing
&& unrelated logic into a slice once 99% of the slices are occupied through
&& related logic packing.
&& Note that once logic distribution reaches the 99% level through related
&& logic packing, this does not mean the device is completely utilized.
&& Unrelated logic packing will then begin, continuing until all usable LUTs
&& and FFs are occupied.& Depending on your timing budget, increased levels of
&& unrelated logic packing may adversely affect the overall timing performance
&& of your design.
本文已收录于以下专栏：
相关文章推荐
用来创建能够和Struts 框架和其他相应的HTML 标签交互的HTML 输入表单
在访问Jav...
lec是独立的不基于任何指定的综合工具
key point mapping
ummapped points有三类
formal functional comparison algorithms
Openstack Neutron using VXLAN
13/04/2014
Linux Networking...
String path = request.getContextPath();
String basePath = request.getScheme()+&://&+request.getServ...
对于新人来说，在SharePoint中使用公式
一阶逻辑是数学家、哲学家、语言学家使用的一种形式演绎系统。它有很多名字包括：一阶谓词演算、低等谓词演算、一阶逻辑的语言或谓词逻辑。不像自然语言如英语，FOL使用由数学结构来解释的完全无歧义的形式语言。...
http://blog.csdn.net/pipisorry/article/details/真值测试Truth value testingall(a[, axis, out, kee...
首先介绍一下什么是Logic Constness和Bitwise Constness，Logic Constness指的是function 后的const修饰，我们只知道这个function被cons...
他的最新文章
讲师：汪剑
讲师：刘道宽
您举报文章：
举报原因：
原文地址：
原因补充：
(最多只允许输入30个字)Xilinx ISE MAP 属性全面研究(l转) - chanon的个人空间 - 中国电子顶级开发网(EETOP)-电子设计论坛、博客、超人气的电子工程师资料分享平台
- Powered by X-Space
Xilinx ISE MAP 属性全面研究(l转)
& 14:55:24
/ 个人分类：
跑ISE的P&R的时候，MAP属性对结果的影响是至关重要的。一直想把这部分内容好好过一遍，今天开出这个帖子，请大家一起监督。因为工作繁忙，先把英文原文放在这里占个座位，一边工作，一边利用空余时间把内容补足。[b]Perform. Timing-Driven Packing and Placement [/b](Advanced)&(Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3A and Spartan-3E devices only)Specifies whether or not to give priority to timing critical paths during packing in the Map process. User-generated timing constraints are used to drive the packing and placement operations. The timing constraints are generally specified in the User Constraints File (UCF) and are annotated onto the design during the Translate process. At the completion of the process, the result is a completely placed design, and the design is ready for routing. If Timing-Driven Packing and Placement is selected in the absence of user timing constraints, the tools will automatically generate and dynamically adjust timing constraints for all internal clocks. This feature is referred to as Performance Evaluation mode. This mode allows the clock performance for all clocks in the design to be evaluated in one pass. The performance achieved by this mode is not necessarily the best possible performance each clock can achieve. Instead it is a balance of performance between all clocks in the design. By default, this property is set to False (checkbox is blank).[color=Red]大家都知道，略[/color][b]Perform. Timing-Driven Packing[/b] (Advanced)&(Virtex and Spartan-II devices only)Specifies whether or not to give priority to timing critical paths during packing in the Map process. User-generated timing constraints are used to drive the packing operation. The timing constraints are generally specified in the User Constraints File (UCF) and are annotated onto the design during the Translate operation. By default, this property is set to False (checkbox is blank), and timing-driven packing is not performed.[color=Red]大家都知道，略[/color][b]Map Effort Level (Advanced)[/b]&(Virtex-II and Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3A and Spartan-3E devices only)Note Available only when Perform. Timing-Driven Packing and Placement is set to True (checkbox is checked). Specifies the effort level you want to apply to the Map process. [color=Red]The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement.[/color] You can set the effort level from Standard (fastest run time) to High (best results). This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set True (checkbox is checked). Select an option from the drop-down list.&- Standard: Gives the fastest run time with the lowest mapping effort. Appropriate for a less complex design.&- Medium: Gives a medium run time with good mapping results.&- High: Gives the longest run time with the best mapping results. Appropriate for a more complex design.By default, this property is set to Medium.[color=Red]大家都知道，略[/color][b]Extra Effort (Advanced)[/b]Map spends additional run time in an effort to meet difficult timing constraints.Note The Extra Effort property is available only when the Map Effort Level is set to High.Select an option from the drop-down list.&- None: No extra effort level is applied.- Normal: Runs until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints.- Continue on Impossible: Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This option focuses on getting close to meeting timing constraints.By default, this property is set to None.[color=Red]大家都知道，略[/color][b]Placer Effort Level (Advanced) (Virtex-5 only)[/b]Specifies the effort level you want to apply to the Map process. The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement. You can set the effort level from Standard (fastest run time) to High (best results).Select an option from the drop-down list.&- Standard: Gives the fastest run time with the lowest mapping effort. Appropriate for a less complex design.&- High: Gives the longest run time with the best mapping results. Appropriate for a more complex design.By default, this property is set to High.[color=Red]大家都知道，略[/color][b]Placer Extra Effort (Advanced) (Virtex-5 only)[/b]This property sets the extra effort level for timing-driven packing.This property is only enabled if the Placer Effort Level is set to High.Select an option from the drop-down list.&- None: No extra effort level is applied.- Normal: Runs until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints.- Continue on Impossible: Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This option focuses on getting close to meeting timing constraints.By default, this property is set to None.[color=Red]大家都知道，略[/color][b]Starting Placer Cost Table (1 - 100) [/b](Advanced)Specifies a mapping initialization value with which to begin the map attempts. Each subsequent attempt is assigned an incremental value based on the mapping initialization value. By default, this property is set to 1. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set to True (checkbox is checked).[color=Red]大家都知道，略[/color][b]Combinatorial Logic Optimization[/b] (Advanced) (Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, Spartan-3A and Spartan-3E devices only)Specifies whether or not to run a process that revisits the combinatorial logic within a design to see if any improvements can be made that will improve the overall quality of results. Timing constraints and logic packing information are considered when this process is run. This property is part of the physical synthesis tools in ISE. By default, this property is set to False (checkbox is blank), and this process is not run on the design. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set to True (checkbox is checked).[color=Red]组合逻辑优化是物理综合的一部分，可以提高整体电路的质量。在执行的优化的时候，同时考虑时序约束和逻辑装箱的制约。[/color][b]Register Duplication[/b] (Advanced) (Not available for Virtex or Spartan-II devices)Specifies whether or not you want to replicate the registers to help control fanout. By default, this property is set to False (checkbox is blank), and register duplication is not performed during timing optimization and fanout control. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set True (checkbox is checked).[color=Red]寄存器复制用于减小扇出，以满足时序约束。[/color][b]Global Optimization[/b] (Advanced) (Virtex-4 and Virtex-5 only)When this property is set to True (checkbox is checked), Map performs global optimization routines on the fully assembled netlist before mapping the design. Global optimization includes logic remapping and trimming, logic and register replication and optimization, and logic replacement of tristates. These routines will extend the runtime of Map because extra processing occurs. By default, this property is set to False (checkbox is blank). With Global Optimization set to True, using Partitions is not recommended, and Formal Verification flows will be negatively affected. Also, certain Map properties are not allowed in conjunction with Global Optimization: neither Trim Unconnected Signals (-u) nor Replicate Logic to Allow Logic Level Reduction (-l) may be set to False when running Global Optimization.[color=Red]全局优化是在MAPPING动作以前对网表进行优化处理，比如逻辑重映射和裁剪，逻辑与寄存器的复制与优化，三态的替换等等。造成的后果是MAP时间变长，同时与RTL的等价性也丧失，因此partition / Fromal verification 都受到负面影响，一些选项也因此关闭。[/color][b]Retiming[/b] (Advanced) (Virtex-4 and Virtex-5 only)When this property is set to True (checkbox is checked), registers are moved forward or backwards through the logic to balance out the delays in a timing path to increase the overall clock frequency. The overall number of registers may be altered due to the processing. By default, this property is set to False (checkbox is blank). This property is available only when the Global Optimization property is set to True (checkbox is checked).[color=Red]retiming通过寄存器的前后移动来平衡时序路径，从而提高全局的时钟频率。[/color][color=Red]前提：打开Global Optimization[/color][b]Equivalent Register Removal [/b](Advanced) (Virtex-4 and Virtex-5 only)When this property is set to True (checkbox is checked), any registers with redundant functionality are examined to see if their removal will increase clock frequencies. By default, this property is set to True (checkbox is checked). This property is available only when the Global Optimization property is set to True (checkbox is checked).&[color=Red]删除等价寄存器：如果发现冗余功能寄存器，则判断将其删除是否可以提高时钟频率。[/color][color=Red]前提：打开Global Optimization[/color][b]Ignore User Timing Constraints[/b]This property controls the use of timing constraints during placement. The primary method of specifying timing requirements is by entering them in the User Constraints File (UCF). For detailed information about timing constraints, see the Constraints Guide. If this property is not selected (checkbox is blank), Map packs and places in accordance with any timing constraints specified in the User Constraints File (UCF). If this property is selected (checkbox is checked), timing constraints in the UCF are ignored when Map runs. Map will proceed as follows: For all devices except Virtex-5, packing and placement will run without timing constraints. The Timing Mode property below will indicate Non Timing Driven mode. For Virtex-5, the setting of the Timing Mode property (described below) determines whether MAP will automatically generate timing constraints to control packing and placement or will run without timing constraints.[color=Red]决定是否忽略用户定义的时序约束（UCF文件）。造成的结果是没有时序约束，或者MAP自动产生时序约束。[/color][color=Red]和下面的timing mode配合使用，我们可以看到其真正用途。[/color][b]Timing Mode[/b]This property is enabled when the Ignore User Timing Constraints property (see above) is selected. Select an option from the drop-down list.- Performance Evaluation (Virtex-5 Only): This selection triggers the "Performance Evaluation" mode. In this mode timing constraints specified in the User Constraints File (UCF) are ignored. Instead, timing constraints for all internal clocks are generated automatically and dynamically adjusted during Map to increase performance. This mode is used to evaluate realistic performance targets for the design. Performance Evaluation is described in the "MAP" chapter in the Development System Reference Guide.- Non Timing Driven: In this mode, timing constraints specified in the UCF are ignored, and packing and placement will run with no timing constraints. This selections will make the Map process run faster, but will not take into account timing constraints while generating the resulting output.[color=Red]对于Virtex-5，可以采用performance evaluation模式来评估设计的最高时钟。所以xilinx的真实意图就是：用户先不加约束，ISE自己来动态调整提高性能，最后推导出最高的工作时钟。对于其他系列device，这个功能不可用，所以也没有操作的价值。[/color][b]Trim Unconnected Signals[/b]Specifies whether or not to trim unconnected components and nets from the design before mapping occurs. Leaving this option blank is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, set this property to False (checkbox is blank) to map unconnected components and nets. By default, this property is set to True (checkbox is checked), and unconnected components and nets are trimmed.&[color=Red]没有连接的信号当然要删除了，且慢！结论不能这么武断。当设计没有完全结束时，会存在大量的未连接信号，这个时候我们也可以跑一遍P&R，从而预估设计所需资源，从而决定是否选择某款FPGA。原文还提到了可以对部分完成的设计提前进行时序验证，这个貌似和是否删除未连接信号无关啊。[/color][b]Replicate Logic to Allow Logic Level Reduction[/b] (Advanced)Specifies whether or not to replicate logic, such that a single driver that drives multiple loads is replicated, and each separate component drives an individual load. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this property is set to True (checkbox is checked), and logic is replicated.[color=Red]赋值逻辑减少层次：当一个逻辑驱动多个负载时，将该逻辑赋值，每个逻辑只驱动一个负载。[/color][color=Red]感觉这样做的话减少了扇出，可以缩小延迟，提高时序性能。[color=SeaGreen]但是原文提到可以“logic level reduction”，不知道是个什么意思？[/color][/color][b]Allow Logic Optimization Across Hierarchy[/b] (Advanced)When this property is set to True (checkbox is checked), Map ignores any Keep Hierarchy properties set for the Synthesize process and Map can perform. optimizations across any hierarchical boundaries. This property is used to preserve the signals that span the hierarchical boundaries for the purpose of simulation, or to ensure that optimizations do not affect of the behavior. of the designs using Partitions. Better timing performance can be attained by performing such optimizations. By default, this property is set to False (checkbox is blank).&&[color=Red]逻辑优化可以跨越层次结构：采用该设置可以令逻辑优化在全局跨越式进行，从而获取更好的时序性能。[/color][color=Red]不采用该选项的理由是：为了仿真维持原有的结构及相关信号；不影响采用partition的设计。[/color][color=Red]按照这个说法，默认情况下其实优化只是在局部进行的，那对于层次间耦合紧密（比如跨越同一时钟周期）的设计来说，还真的有些问题。[/color][b]Map to Input Functions[/b] (Advanced)Specifies the maximum size of functions covered for FPGA architectures. Select a function between 4 (F4MUX) and 8 (F8MUX) from the drop-down list. By default, this option is set to 6 for Virtex-5 devices, and 4 for all other devices.&[color=Red]选择功能块的最大尺寸：从字面意思看应该是选择LUT4或者LUT6之类意思，按照我的了解，V5以前的主要是LUT4，那么选大于4的值的话，应该是要两个LUT4组合起来构成一个大的LUT才行。由于V5是采用LUT6所以可以看到他的默认值也是6。这个值应该采用默认即可，除非你的逻辑块的输入都是固定的5输入、6输入之类的应用，那样的话，可以专门设置一下。[/color][b]Optimization Strategy[/b] (Cover Mode) (Advanced)Specifies the criteria used during the "cover" phase of MAP. In the "cover" phase, MAP assigns the logic to CLB function generators (LUTs). Select an option from the drop-down list.&- Area: Select Area to make reducing the number of LUTs (and therefore the number of CLBs) the highest priority.- Speed: Select Speed to make reducing the number of levels of LUTS (the number of LUTs a path passes through) the highest priority. This setting makes it easiest to achieve your timing constraints after the design is placed and routed. For most designs there is a small increase in the number of LUTs (compared to the area setting), and in some cases the increase may be large.- Balanced: Select Balanced to ba reducing the number of LUTs and reducing the number of levels of LUTs. The Balanced option produces results similar to the Speed setting but avoids the possibility of a large increase in the number of LUTs.- Off: Select Off to disable optimization.By default, this property is set to Area.[color=Red]优化策略：面积优先或者时序优先，或者两者平衡或者都不采用，面积和时序互相制约，面积大点则时序增强，反之亦然。[/color][color=Red]这个优化发生在MAP的cover阶段，将逻辑赋值给LUT。[/color][color=Red]推荐：使用balanced比较好，性能上接近时序优先，但是面积又不会变很大。[/color][b]Generate Detailed MAP Report[/b]Specifies whether or not to display a detailed report. A detailed Map Report displays redundant blocks that were removed and signals that were merged during the mapping process. It also displays expanded logic, signal cross-references, and symbol cross-references. By default, this property is set to False (checkbox is blank), and a detailed Map Report is not generated.[color=Red]产生详细MAP报告：默认关闭该选项，看需要自己决定吧。[/color][b]Use RLOC Constraints[/b] (Advanced)Specifies whether or not to use the RLOC information that contains the relative placement of one CLB to another. By default, this property is set to True (checkbox is checked), and MAP uses the RLOC information, even invalid information that could result in a Map process error.[color=Red]RLOC约束定义了CLB之间的location关系，这个不太了解，不乱讲了。[/color][b]Pack I/O Registers/Latches into IOBs[/b]Controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. Select an option from the drop-down list.&- Off: Select Off to pack flip-flops or latches as specified by your design entry method.- For Inputs Only: Select Inputs Only to pack flip-flops or latches into input I/O cells.- For Outputs Only: Select Outputs Only to pack flip-flops or latches into output I/O cells.- For Inputs and Outputs: Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.By default, this property is set to Off for Virtex-5 devices, and For Inputs and Outputs for all other devices.[color=Red]将寄存器锁存器打包到IOB内。这么做的优点是可以令输入和输出的延迟最小，因为输入输出信号都是直接从IOB走的，FPGA内再也没有别的延迟（IDELAY和ODELAY除外）。而如果没有打包入IOB的话，信号从寄存器出来后还要经过IOB延迟一下，这个影响还是比较大的。所以以前有这样的建议，就是将输入输出全部用寄存器处理，同时寄存器都pack到IOB，这样，input delay和output delay就不用再约束了，因为已经是最小的了。[/color][b]Disable Register Ordering[/b] (Advanced)Controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. By default, this property is set to Off (checkbox is blank).[color=Red]寄存器排序，这个处理用于优化寄存器在CLB内的grouping。[/color][color=Red]我不知道这个优化的具体含义，以后了解了再补充。[/color][b]Maximum Compression[/b] (Advanced) (Virtex-5 only)When set to True (checkbox is checked), this option instructs Map to pack the design logic as densely as possible. This is done at the risk of negative place and route performance. By default, this property is set to False (checkbox is blank).[color=Red]最大压缩，这个操作令MAP将逻辑块紧密压缩，可以减小FPGA面积，但是对布局布线是个不小的挑战。[/color][b]CLB Pack Factor Percentage[/b] (Advanced)Specifies how densely logic will be partitioned using a percentage value. A higher percentage number will result in lower density packing. A high CLB pack factor percentage can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Note This property is not available for Virtex-5 devices. The command line equivalent to setting this property is -c [packfactor], where packfactor is the percentage of CLBs available in a target device for packing your designs logic. Enter a numeric value in this property. By default, this property is set to 100 (%) which means that all CLBs in a target part are available for design logic. This property is grayed out and cannot be set when either the Perform. Timing-Driven Packing and Placement property is set True (checkbox is checked) or the Perform. Timing-Driven Packing property is set True (checkbox is checked).[color=Red]CLB PACK 百分比，这个概念不是很清楚。总之数值越大，逻辑布局会越分散，对布局布线的影响越不利。[/color][color=Red]采用time-driven的P&R方式的话，这个选项是关闭的。客观的讲，这个选项不是给一般用户使用的。[/color][b]Tri-state Buffer Transformation Mode[/b] (Advanced)Specifies the type of bus transformation that Map will perform. Note This property is not available for Virtex-5, Virtex-4, Spartan-3, or Spartan-3E devices because tri-state buffer transformations are performed automatically for these devices. Select one of the options from the drop-down list.&-Off: Does not transform. tristate buses.- On: Transforms tristate buses to LUT or CY logic, as necessary.- Aggressive: Transforms all tristate buses to LUT or CY logic.- Limit: Transforms only the portions of buses that exceed the device limitations.By default, this property is set to Off.[color=Red]三态缓存模式，用于定义三态总线的实现方式，比如LUT或者CY逻辑。[/color][b]LUT Combining[/b] (Advanced) (Virtex-5 only)LUT combining enables the merging of LUT pairs with common inputs into single dual-output 6-input LUTs in order to improve design area. This optimization process may reduce design speed. Select one of the options from the drop-down list.&- No: Disables LUT combining.- Auto: Map tries to make a tradeoff between area and speed.- Area: Map performs maximum LUT combining to provide as small an implementation as possible.By default, this property is set to Off.[color=Red]LUT组合，这个选项只在V5中提供，作用是将相同输入的两个LUT用一个 “双输出LUT-6” 来替代。[/color][color=Red]目的很明确，就是要精简面积，当然对时序的影响是消极的。[/color][b]Map Slice Logic into Unused Block RAMs[/b] (Advanced)Specifies whether or not MAP attempts to place LUTs and flip-flops into Block RAMs. By default, this property is set to False (checkbox is blank).[color=Red]MAP是否将slice逻辑放入BRAM中，不知道这样做的优势在哪里？[/color][color=Red]（看来ISE的帮助文档写得也不完整啊，这种必需解答的问题没有解答，用户怎么敢轻易使用这些选项）。[/color][b]Power Reduction[/b] (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 only)If enabled, Map will optimize placement during timing-driven packing and placement to reduce the power consumed by the design. This property is enabled when the Perform. Timing-Driven Packing and Placement property is set enabled (checkbox is checked). By default, this property is disabled.[color=Red]功率削减，这个选项可以帮助设计降低功耗。[/color][color=Red]前提：Perform. Timing-Driven Packing and Placement[/color][b]Power Activity File[/b] (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 only)This property allows you to specify a simulation file, *.vcd or *.saif, to guide Map when it optimizes the design for power reduction. This file is the output of a simulation run on the design. For power reduction, Map uses this file to set frequencies and activity rates of internal signals, which are signals that are not inputs or outputs but internal to the design. Note Simulation is the most accurate method of determining the exact activity rates. Back-annotated post-place and route simulation provides the best data for determining activity rates since it most closely represents physical implementation. By default, this property is blank (no file name).[color=Red]功率活动文件，这个文件来自仿真（应该是后仿真，否则内部信号如何匹配）的输出，格式为*.vcd或者*.saif。[/color][color=Red]由于仿真文件包含了典型的scenario，因此可以为ISE提供每个内部信号的活动频率，指导上述功率削减过程。[/color][color=Red]ISE根据仿真文件判断内部功耗较大和较小的部分。至于如何进行功率削减，文档没有提及，我们看些资料再谈这个问题吧。[/color][b]Other Map Command Line Options [/b](Advanced)Enter additional command line options. Multiple options are separated with a space. The options entered in this property appear first on the command line, before all other property options specified in the graphical user interface. Avoid setting duplicate property options. For more information about command line options, see the Development System Reference Guide.Copyright&&2008, Xilinx Inc. All rights reserved.