ISPLSI1032E-70LJI (LATTICE) PDF技术资料下载
ISPLSI1032E-70LJI 供应信息 IC Datasheet 数据表 (1/16 页)
按型号查询：
ISPLSI1032E-70LJI
高密度可编程逻辑
[High-Density Programmable Logic]
&&ISPLSI1032E-70LJIPDF文件：
高密度可编程逻辑[High-Density Programmable Logic]
文件大小：&&213 KPDF页数：
&&16 页联系供应商：&& 品牌Logo:
&&&&LATTICE [ LATTICE SEMICONDUCTOR ]
ISPLSI1032E-70LJI&&
ISPLSI1032E-70LJI&&
ISPLSI1032E-70LJI&&
ISPLSI1032E-70LJI&&
ispLSI and pLSI 1032E(R)(R)High-Density Programmable LogicFeatureso HIGH DENSITY PROGRAMMABLE LOGIC— 6000 PLD Gates— 64 I/O Pins, Eight Dedicated Inputs— 192 Registers— High Speed Global Interconnect— Wide Input Gating for Fast Counters, StateMachines, Address Decoders, etc.— Small Logic Block Size for Random Logico HIGH PERFORMANCE E2CMOS(R)TECHNOLOGY—fmax= 125 MHz Maximum Operating Frequency—tpd= 7.5 ns Propagation Delay— TTL Compatible Inputs and Outputs— Electrically Erasable and Reprogrammable— Non-Volatile— 100% Tested at Time of Manufacture— Unused Product Term Shutdown Saves Powero ispLSI OFFERS THE FOLLOWING ADDED FEATURES— In-System Programmable (ISP(TM)) 5-Volt Only— Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality— Reprogram Soldered Devices for Faster Prototypingo OFFERS THE EASE OF USE AND FAST SYSTEMSPEED OF PLDs WITH THE DENSITY AND FLEXIBILITYOF FIELD PROGRAMMABLE GATE ARRAYS— Complete Programmable Device Can Combine GlueLogic and Structured Designs— Enhanced Pin Locking Capability— Four Dedicated Clock Input Pins— Synchronous and Asynchronous Clocks— Programmable Output Slew Rate Control toMinimize Switching Noise— Flexible Pin Placement— Optimized Global Routing Pool Provides GlobalInterconnectivityo ispEXPERT(TM) – LOGIC COMPILER AND COMPLETEISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESISTHROUGH IN-SYSTEM PROGRAMMING— Superior Quality of Results— Tightly Integrated with Leading CAE Vendor Tools— Productivity Enhancing Timing Analyzer, ExploreTools, Timing Simulator and ispANALYZER(TM)— PC and UNIX PlatformsFunctional Block DiagramOutput Routing PoolD7 D6 D5 D4 D3 D2 D1 D0A0D QC7Output Routing PoolA2A3A4A5A6A7D QLogicArrayC5D QGLBC4C3D QC2C1Global Routing Pool (GRP)B0 B1 B2 B3 B4 B5 B6 B7Output Routing PoolC0CLKDescriptionThe ispLSI and pLSI 1032E are High Density Program-mable Logic Devices containing 192 Registers, 64Universal I/O pins, eight Dedicated Input pins, four Dedi-cated Clock Input pins and a Global Routing Pool (GRP).The GRP provides complete interconnectivity betweenall of these elements. The ispLSI 1032E features 5-Voltin-system programmability and in-system diagnostic ca-pabilities. The ispLSI 1032E device offers non-volatilereprogrammability of the logic, as well as the intercon-nects to provide truly reconfigurable systems. It isarchitecturally and parametrically compatible to the pLSI1032E device, but multiplexes four input pins to controlin-system programming. A functional superset of theispLSI and pLSI 1032 architecture, the ispLSI and pLSI1032E devices add two new global output enable pins.The basic unit of logic on the ispLSI and pLSI 1032Edevices is the Generic Logic Block (GLB). The GLBs arelabeled A0, A1…D7 (see Figure 1). There are a total of 32GLBs in the ispLSI and pLSI 1032E devices. Each GLBhas 18 inputs, a programmable AND/OR/Exclusive ORarray, and four outputs which can be configured to beeither combinatorial or registered. Inputs to the GLBcome from the GRP and dedicated inputs. All of the GLBoutputs are brought back into the GRP so that they canbe connected to the inputs of any GLB on the device.Copyright (C) 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subjectto change without notice.LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.Tel. (503) 681--LATTICE; FAX (503) 681-3037; October 19981032E_061Output Routing Pool0139A(A1)-ispA1C6(LATTICE) PDF技术资料下载
供应信息 IC Datasheet 数据表 (1/16 页)
按型号查询：
高密度可编程逻辑
[High-Density Programmable Logic]
&&PDF文件：
高密度可编程逻辑[High-Density Programmable Logic]
文件大小：&&213 KPDF页数：
&&16 页联系供应商：&& 品牌Logo:
&&&&LATTICE [ LATTICE SEMICONDUCTOR ]
ispLSI and pLSI 1032E(R)(R)High-Density Programmable LogicFeatureso HIGH DENSITY PROGRAMMABLE LOGIC— 6000 PLD Gates— 64 I/O Pins, Eight Dedicated Inputs— 192 Registers— High Speed Global Interconnect— Wide Input Gating for Fast Counters, StateMachines, Address Decoders, etc.— Small Logic Block Size for Random Logico HIGH PERFORMANCE E2CMOS(R)TECHNOLOGY—fmax= 125 MHz Maximum Operating Frequency—tpd= 7.5 ns Propagation Delay— TTL Compatible Inputs and Outputs— Electrically Erasable and Reprogrammable— Non-Volatile— 100% Tested at Time of Manufacture— Unused Product Term Shutdown Saves Powero ispLSI OFFERS THE FOLLOWING ADDED FEATURES— In-System Programmable (ISP(TM)) 5-Volt Only— Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality— Reprogram Soldered Devices for Faster Prototypingo OFFERS THE EASE OF USE AND FAST SYSTEMSPEED OF PLDs WITH THE DENSITY AND FLEXIBILITYOF FIELD PROGRAMMABLE GATE ARRAYS— Complete Programmable Device Can Combine GlueLogic and Structured Designs— Enhanced Pin Locking Capability— Four Dedicated Clock Input Pins— Synchronous and Asynchronous Clocks— Programmable Output Slew Rate Control toMinimize Switching Noise— Flexible Pin Placement— Optimized Global Routing Pool Provides GlobalInterconnectivityo ispEXPERT(TM) – LOGIC COMPILER AND COMPLETEISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESISTHROUGH IN-SYSTEM PROGRAMMING— Superior Quality of Results— Tightly Integrated with Leading CAE Vendor Tools— Productivity Enhancing Timing Analyzer, ExploreTools, Timing Simulator and ispANALYZER(TM)— PC and UNIX PlatformsFunctional Block DiagramOutput Routing PoolD7 D6 D5 D4 D3 D2 D1 D0A0D QC7Output Routing PoolA2A3A4A5A6A7D QLogicArrayC5D QGLBC4C3D QC2C1Global Routing Pool (GRP)B0 B1 B2 B3 B4 B5 B6 B7Output Routing PoolC0CLKDescriptionThe ispLSI and pLSI 1032E are High Density Program-mable Logic Devices containing 192 Registers, 64Universal I/O pins, eight Dedicated Input pins, four Dedi-cated Clock Input pins and a Global Routing Pool (GRP).The GRP provides complete interconnectivity betweenall of these elements. The ispLSI 1032E features 5-Voltin-system programmability and in-system diagnostic ca-pabilities. The ispLSI 1032E device offers non-volatilereprogrammability of the logic, as well as the intercon-nects to provide truly reconfigurable systems. It isarchitecturally and parametrically compatible to the pLSI1032E device, but multiplexes four input pins to controlin-system programming. A functional superset of theispLSI and pLSI 1032 architecture, the ispLSI and pLSI1032E devices add two new global output enable pins.The basic unit of logic on the ispLSI and pLSI 1032Edevices is the Generic Logic Block (GLB). The GLBs arelabeled A0, A1…D7 (see Figure 1). There are a total of 32GLBs in the ispLSI and pLSI 1032E devices. Each GLBhas 18 inputs, a programmable AND/OR/Exclusive ORarray, and four outputs which can be configured to beeither combinatorial or registered. Inputs to the GLBcome from the GRP and dedicated inputs. All of the GLBoutputs are brought back into the GRP so that they canbe connected to the inputs of any GLB on the device.Copyright (C) 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subjectto change without notice.LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.Tel. (503) 681--LATTICE; FAX (503) 681-3037; October 19981032E_061Output Routing Pool0139A(A1)-ispA1C61032E-70LJ 电子技术资料PDF资料下载 第1页, 高密度可编程逻辑
电子数据表 IC PDF
datasheet 1032E-70LJ datasheets manu [LATTICE] - -
电子元器件数据表 IC PDF查询
1032E-70LJ&高密度可编程逻辑 (High-Density Programmable Logic)
&&1032E-70LJ
&&&鼠标右键选目标另存为
&&&不需安装PDF阅读软件
高密度可编程逻辑High-Density Programmable Logic
文件大小 ：
&&213 K&&&&
&& [ LATTICE SEMICONDUCTOR ]
1032E-70LJ&高密度可编程逻辑 (High-Density Programmable Logic)
可编程逻辑器件和PLSI 1032E(R)(R)高密度可编程逻辑特点o高密度可编程逻辑- 6000 PLD门- 64个I / O引脚，八个专用输入- 192寄存器- 高速全球互联- 宽输入选通高速计数器，国家机，地址解码器等- 小逻辑块大小为随机逻辑o高性能ê2CMOS(R)技术—f最大= 125 MHz的最高工作频率—tpd= 7.5 ns的传播延迟o TTL兼容的输入和输出- 电可擦除和可重复编程- 非易失性- 100％测试在制造时- 未使用的产品长期关机节省电源o可编程逻辑器件提供了以下新增功能- 在系统可编程（ ISP (TM) ） 5伏只有- 提高生产良率，减少时间用于─市场和提高产品质量- 重新编程锡焊设备进行快速原型o提供使用和快速的系统的易用性可编程逻辑器件速度与密度和灵活性现场可编程门阵列- 完整的可编程器件可以结合胶逻辑和结构化设计- 增强的引脚锁定功能- 四个专用时钟输入引脚- 同步和异步时钟- 可编程的输出压摆率控制，以最大限度地降低开关噪声- 灵活的引脚布局- 优化的全球路由池提供全球互联o ispEXPERT (TM) - 逻辑编译器和完整ISP器件设计系统免受高密度脂蛋白合成通过在线编程- 业绩卓越的品质- 紧密集成了领先的CAE供应商工具- 提高生产率的时序分析，探索工具，时序仿真和ispANALYZER (TM)- PC和UNIX平台功能框图输出路由池D7 D6 D5 D4 D3 D2 D1 D0A0? QC7输出路由池A2A3A4A5A6A7? Q逻辑ARRAYC5? QGLBC4C3? QC2C1全球路由池（ GRP ）B0 B1 B2 B3 B4 B5 B6 B7输出路由池C0CLK描述在系统可编程逻辑器件和PLSI 1032E是高密度编程含192寄存器，64个的可编程逻辑器件通用I / O引脚，八个专用输入引脚， 4德迪cated时钟输入引脚和一个全球路由池（ GRP ） 。玻璃钢之间提供完整的互连所有这些元素。在系统可编程逻辑器件1032E提供5伏在系统编程和在系统诊断钙pabilities 。在系统可编程逻辑器件1032E设备提供非易失性逻辑的可重编程，以及在互连nects提供真正的可重构系统。这是建筑和参兼容的PLSI1032E设备，但复用四个输入引脚来控制在系统编程。的功能性超可编程逻辑器件和PLSI 1032架构，可编程逻辑器件和PLSI1032E设备添加两个新的全球输出使能引脚。逻辑上的可编程逻辑器件和PLSI 1032E的基本单位设备是通用逻辑块（ GLB ） 。该GLBs是标记A0，A1 ... D7 （参见图1） 。总共有32是GLBs在系统可编程逻辑器件和PLSI 1032E设备。每个GLB有18个输入，一个可编程的与/或/异或其可以被构造为阵列，和四个输出无论组合或注册。投入到GLB来自GRP和专用输入。所有的GLB输出带回的GRP使他们能够被连接到任意GLB的设备上的输入。版权所有(C)1998莱迪思半导体公司的所有品牌或产品名称均为其各自所有者的注册商标。此处的规格和信息如有更改，恕不另行通知。莱迪思半导体股份有限公司， 5555东北摩尔的Ct 。 ，俄勒冈州希尔斯伯勒97124 ， USA电话： （ 503 ） 681-0118 ; 1-800- LATTICE ;传真（ 503 ） 681-3037 ; 1998年10月1032E_061输出路由池0139A(A1)-ispA1C6
Copyright(C) 2001 - 2014
ICPDF All RightsLJ中文资料_图文_百度文库
两大类热门资源免费畅读
续费一年阅读会员，立省24元！
LJ中文资料
电子元器件行业，实体市场，全程保障|
总评分0.0|
阅读已结束，下载文档到电脑
想免费下载本文？
定制HR最喜欢的简历
下载文档到电脑，方便使用
还剩13页未读，继续阅读
定制HR最喜欢的简历
你可能喜欢ISPLSILJ (LATTICE) PDF技术资料下载
ISPLSILJ 供应信息 IC Datasheet 数据表 (1/16 页)
按型号查询：
高密度可编程逻辑
[High-Density Programmable Logic]
&&ISPLSILJPDF文件：
高密度可编程逻辑[High-Density Programmable Logic]
文件大小：&&213 KPDF页数：
&&16 页联系供应商：&& 品牌Logo:
&&&&LATTICE [ LATTICE SEMICONDUCTOR ]
ISPLSILJ&&
保证原装正品、假一赔十&
ISPLSILJ&&
ISPLSILJ&&
ISPLSILJ&&
ispLSI and pLSI 1032E(R)(R)High-Density Programmable LogicFeatureso HIGH DENSITY PROGRAMMABLE LOGIC— 6000 PLD Gates— 64 I/O Pins, Eight Dedicated Inputs— 192 Registers— High Speed Global Interconnect— Wide Input Gating for Fast Counters, StateMachines, Address Decoders, etc.— Small Logic Block Size for Random Logico HIGH PERFORMANCE E2CMOS(R)TECHNOLOGY—fmax= 125 MHz Maximum Operating Frequency—tpd= 7.5 ns Propagation Delay— TTL Compatible Inputs and Outputs— Electrically Erasable and Reprogrammable— Non-Volatile— 100% Tested at Time of Manufacture— Unused Product Term Shutdown Saves Powero ispLSI OFFERS THE FOLLOWING ADDED FEATURES— In-System Programmable (ISP(TM)) 5-Volt Only— Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality— Reprogram Soldered Devices for Faster Prototypingo OFFERS THE EASE OF USE AND FAST SYSTEMSPEED OF PLDs WITH THE DENSITY AND FLEXIBILITYOF FIELD PROGRAMMABLE GATE ARRAYS— Complete Programmable Device Can Combine GlueLogic and Structured Designs— Enhanced Pin Locking Capability— Four Dedicated Clock Input Pins— Synchronous and Asynchronous Clocks— Programmable Output Slew Rate Control toMinimize Switching Noise— Flexible Pin Placement— Optimized Global Routing Pool Provides GlobalInterconnectivityo ispEXPERT(TM) – LOGIC COMPILER AND COMPLETEISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESISTHROUGH IN-SYSTEM PROGRAMMING— Superior Quality of Results— Tightly Integrated with Leading CAE Vendor Tools— Productivity Enhancing Timing Analyzer, ExploreTools, Timing Simulator and ispANALYZER(TM)— PC and UNIX PlatformsFunctional Block DiagramOutput Routing PoolD7 D6 D5 D4 D3 D2 D1 D0A0D QC7Output Routing PoolA2A3A4A5A6A7D QLogicArrayC5D QGLBC4C3D QC2C1Global Routing Pool (GRP)B0 B1 B2 B3 B4 B5 B6 B7Output Routing PoolC0CLKDescriptionThe ispLSI and pLSI 1032E are High Density Program-mable Logic Devices containing 192 Registers, 64Universal I/O pins, eight Dedicated Input pins, four Dedi-cated Clock Input pins and a Global Routing Pool (GRP).The GRP provides complete interconnectivity betweenall of these elements. The ispLSI 1032E features 5-Voltin-system programmability and in-system diagnostic ca-pabilities. The ispLSI 1032E device offers non-volatilereprogrammability of the logic, as well as the intercon-nects to provide truly reconfigurable systems. It isarchitecturally and parametrically compatible to the pLSI1032E device, but multiplexes four input pins to controlin-system programming. A functional superset of theispLSI and pLSI 1032 architecture, the ispLSI and pLSI1032E devices add two new global output enable pins.The basic unit of logic on the ispLSI and pLSI 1032Edevices is the Generic Logic Block (GLB). The GLBs arelabeled A0, A1…D7 (see Figure 1). There are a total of 32GLBs in the ispLSI and pLSI 1032E devices. Each GLBhas 18 inputs, a programmable AND/OR/Exclusive ORarray, and four outputs which can be configured to beeither combinatorial or registered. Inputs to the GLBcome from the GRP and dedicated inputs. All of the GLBoutputs are brought back into the GRP so that they canbe connected to the inputs of any GLB on the device.Copyright (C) 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subjectto change without notice.LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.Tel. (503) 681--LATTICE; FAX (503) 681-3037; October 19981032E_061Output Routing Pool0139A(A1)-ispA1C6