内存金邦ddr3 1333 4G 的 用cpuZ 测试内存频率是680.0MHz左右 正常吗 应该是667 吧_百度知道
内存金邦ddr3 1333 4G 的 用cpuZ 测试内存频率是680.0MHz左右 正常吗 应该是667 吧
我有更好的答案
你好楼主非常正常这是因为节能的情况,所以内存自动降频来减少扯电..等等一般降多少,都是取决以你目前的电脑工作量来算 你玩游戏 当然会自动提升至1333M 你待机上网等,会自动降到最适合的频率
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您所在的位置：&&&&DDR SDRAM
　　DDR(Double Data Rate) S就是双倍数据传输率的。DDR是更先进的SD。SDRAM只在时钟周期的上升沿传输指令、地址和数据。而DDR内存的有特殊的电路，可以让它在时钟的上、下沿都传输数据。
　　DDR内存是更先进的SDRAM。SDRAM只在时钟周期的上升沿传输指令、地址和数据。而DDR内存的数据线有特殊的电路，可以让它在时钟的上、下沿都传输数据。所以DDR在每个时钟周期可以传输两个数据，而SDRAM只能传输一个数据。举例来说，DDR266能提供266 MHz×2×4 B＝2.1 GB/s的内存带宽。另外，由于它是基于SDRAM的设计制造技术，因此厂房、流水线等设备的更新成本可降到最低。这就使得DDR SDRAM的价格比普通的SDRAM贵不了多少(10％)。因此，DDR SDRAM在当前得到了非常广泛的应用。
与SDRAM的区别
　　DDR SDRAM与SDRAM的不同主要体现在以下几个方面：
　　(1) 初始化。SDRAM在开始使用前要进行初始化，这项工作主要是对模式寄存器进行设置，即MRS。DDR SDRAM与SDRAM一样，在开机时也要进行MRS，不过由于操作功能的增多，DDR SDRAM在MRS之前还增加了一个扩展模式寄存器设置(EMRS)过程。这个扩展模式寄存器对DLL的有效与禁止、输出驱动强度等功能实施控制。
　　(2) 时钟。前面介绍SDRAM时已经看到，SDRAM的读/写采用单一时钟。在DDR SDRAM工作中要用差分时钟，也就是两个时钟，一个是CLK，另一个是与之反相的CK#。
　　CK#并不能被理解为第二个触发时钟(可以在讲述DDR原理时简单地这么比喻)，它能起到触发时钟校准的作用。由于数据是在CLK的上下沿触发的，造成传输周期缩短了一半，因此必须要保证传输周期的稳定以确保数据的正确传输，这就要求对CLK的上下沿间距要有精确的控制。但因为温度、电阻性能的改变等原因，CLK上下沿间距可能发生变化，此时与其反相的CK#就起到纠正的作用(CLK上升快下降慢，CK#则是上升慢下降快)。而由于上下沿触发的原因，也使CL＝1.5或2.5成为可能，并容易实现。
　　(3) 数据选取(DQS)脉冲。DQS是DDR SDRAM中的重要信号，其功能主要用来在一个时钟周期内准确地区分出每个传输周期，并使数据得以准确接收。每一块DDR SDRAM芯片都有一个双向的DQS信号线。在写入时，它用来传送由北桥发来的DQS信号；在读取时，则由芯片生成DQS向北桥发送。可以说，DQS就是数据的同步信号。
　　(4) 写入延时。在写入时，与SDRAM的0延时不一样，DDRSDRAM的写入延迟已经不是0了。在发出写入命令后，DQS与写入数据要等一段时间才会送达。这个周期被称为DQS相对于写入命令的延迟时间。
　　为什么会有这样的延迟呢？原因也在于同步，毕竟在一个时钟周期内进行两次传送需要很高的控制精度，它必须要等接收方做好充分的准备才行。tDQSS是DDR内存写入操作的一个重要参数，太短的话恐怕接收有误，太长则会造成总线空闲。tDQSS最短不能小于0.75个时钟周期，最长不能超过1.25个时钟周期。
　　(5) 突发长度与写入掩码。在DDR SDRAM中，突发长度只有2、4、8三种选择，没有了SDRAM的随机存取的操作(突发长度为1)和全页式突发方式。同时，突发长度的定义也与SDRAM的不一样了，它不再指所连续寻址的存储单元数量，而是指连续的传输周期数。
　　对于突发写入，如果其中有不想存入的数据，仍可以运用DM信号进行屏蔽。DM信号和数据信号同时发出，接收方在DQS的上升沿与下降沿来判断DM的状态，如果DM为高电平，那么之前从DQS脉冲中部选取的数据就被屏蔽了。
　　（6）延迟锁定回路(DLL)。DDR SDRAM对时钟的精确性有着很高的要求，而DDR SDRAM有两个时钟，一个是外部的总线时钟，一个是内部的工作时钟。在理论上，DDRSDRAM的这两个时钟应该是同步的，但由于种种原因，如温度、电压波动而产生延迟使两者很难同步，更何况时钟频率本身也有不稳定的情况。这就需要根据外部时钟动态修正内部时钟的延迟来实现内部时钟与外部时钟的同步，为此专门设置了DLL。利用这种电路，可使内部时钟与外部时钟保持同步。
　　(1) 读出。DDR SDRAM的读出时序关系与SDRAM很相似，如图所示。
　　(2) 写入。突发写入的时序如图所示。
　　在图中表示的是突发写入的过程，突发长度为4。由图我们注意到，在写入第一个数据前有一段写入延时tDQSS。
　　同样，DDR SDRAM是每个时钟周期写入两个数据。
　　最后要说明的是，为了使用户用好DDR SDRAM，厂家为我们开发了有关的控制器芯片，在将来连接使用时注意去选用。在PC机中，厂家开发出支持DDR SDRAM的北桥芯片，该芯片能提供DDR SDRAM工作所要求的信号，这为用户提供了很大的方便。
　　目前，PC机上的内存条主要是由SDR SDRAM(单倍速率同步DRAM)或DDR SDRAM芯片构成的。
　　标准的DDR内存条是184引脚线 DIMM(双面引脚内存条)。它很像标准的168引脚线 SDRAM DIMM，只是用了一个凹槽而不是SD上的两个凹槽。组件的长度也是5.25英寸。
　　标准化协会定义了两种不同配置的DDR内存条。第一种是无缓冲DDR DIMM，它成本低，可应用在PC和Internet设备上。
　　第二种是有缓冲DDR DIMM，应用于较高存储密度的服务器中。
　　新近的DDR-Ⅱ内存条所用的DDR芯片的速度更高一些。目前有三种工作频率：400 MHz、533 MHz和667 MHz，可以达到的速率分别为4.8 GB/s、5.6 GB/s和6.4 GB/s。所有的DDR-Ⅱ内存条均工作在1.8 V电压之下，单条容量均在512 MB以上。
　　DDR-Ⅱ内存条的引脚线有200线、220线和240线几种。
结构与接口定义
　　VDD、VDDQ：电源供电
　　CLK、/CLK:差分时钟
　　CKE:时钟使能
　　/CS：片选信号
　　BA0-BA1:块选择（决定哪个块进行读、写、刷新、预充电等操作）
　　/RAS：行地址选取
　　/CAS：列地址选取
　　A0-A11:地址
　　DQ0-DQ15:双向数据
　　DQS:数据选通信号，控制I/O buffer，数据真正的同步信号
　　/WE ：读/写信号，高电平为读命令，低电平为写命令
　　DM、/DM：数据标志位，标示当前数据是否为有效数据
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Details, datasheet, quote on part number: MT41J256M16RE-15E IT:D
PartMT41J256M16RE-15E IT:D
CategoryIntegrated Circuits (ICs)
TitleMemory Integrated Circuit (ics) DDR3 SDRAM Bulk 1.425 V ~ 1.575 V
Description
CompanyMicron Technology, Inc
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Specifications&
Memory TypeDDR3 SDRAM
Memory Size4G (256M x 16)
Speed667MHz
InterfaceParallel (Byte-wide)
Package / Case96-TFBGA
PackagingBulk
Voltage - Supply1.425 V ~ 1.575 V
Operating Temperature-40°C ~ 95°C
Format - MemoryRAM
Lead Free StatusLead Free
RoHS StatusRoHS Compliant
Features, Applications
VDD = V DDQ ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS READ latency (CL) Posted CAS additive latency (AL) Programmable CAS WRITE latency (CWL) based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable or BL8 on-the-fly (OTF) Self refresh mode 64ms, 8192 cycle refresh 32ms, 8192 cycle refresh to 95°C Self refresh temperature (SRT) Write leveling Multipurpose register Output driver calibration
Configuration - 1 Gig - 512 Meg - 256 Meg x 16 FBGA package (Pb-free) x 12mm) Rev. x 10.5mm) Rev. E FBGA package (Pb-free) x 14mm) Rev. x 14mm) Rev. E Timing - cycle time 7 (DDR3-1066) Operating temperature - Commercial +95°C) - Industrial C +95°C) Revision
1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings.
Backward compatible 7 (-187E). Backward compatible 9 (-15E). Backward compatible 11 (-125). Backward compatible 13 (-107).
Micron Technology, Inc. reserves the right to change products or specifications without notice. 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size 1 Gig 4 128 Meg banks 1KB 512 Meg 8 64 Meg banks 1KB 256 Meg 16 32 Meg x 8 banks (A[9:0]) 2KB
Example Part Number: MT41J512M8RA-15E:D MT41J Configuration Package Speed : Revision
:D/:E Temperatu 512M8 256M16 Speed Grade Package x 12mm FBGA x 10.5mm FBGA x 14mm FBGA x 14mm FBGA Rev. Mark -15E -187E
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron's Web site: http://www.micron.com.
State Diagram................................................................................................................................................ 11 Functional Description................................................................................................................................... 12 Industrial Temperature............................................................................................................................... 12 General Notes............................................................................................................................................ 12 Functional Block Diagrams............................................................................................................................. 14 Ball Assignments and Descriptions................................................................................................................. 17 Package Dimensions....................................................................................................................................... 23 Electrical Specifications.................................................................................................................................. 27 Absolute Ratings......................................................................................................................................... 27 Input/Output Capacitance.......................................................................................................................... 28 Thermal Characteristics.................................................................................................................................. 29 Electrical Specifications - IDD Specifications and Conditions............................................................................ 30 Electrical Characteristics - IDD Specifications.................................................................................................. 41 Electrical Specifications - DC and AC.............................................................................................................. 45 DC Operating Conditions........................................................................................................................... 45 Input Operating Conditions........................................................................................................................ 45 AC Overshoot/Undershoot Specification..................................................................................................... 48 Slew Rate Definitions for Single-Ended Input Signals................................................................................... 52 Slew Rate Definitions for Differential Input Signals...................................................................................... 54 Output Driver Impedance............................................................................................................................... 55 34 Ohm Output Driver Impedance.............................................................................................................. 56 34 Ohm Driver............................................................................................................................................ 57 34 Ohm Output Driver Sensitivity................................................................................................................ 58 Alternative 40 Ohm Driver.......................................................................................................................... 59 40 Ohm Output Driver Sensitivity................................................................................................................ 59 Output Characteristics and Operating Conditions............................................................................................ 61 Reference Output Load............................................................................................................................... 63 Slew Rate Definitions for Single-Ended Output Signals................................................................................. 64 Slew Rate Definitions for Differential Output Signals.................................................................................... 65 Speed Bin Tables............................................................................................................................................ 66 Electrical Characteristics and AC Operating Conditions................................................................................... 71 Command and Address Setup, Hold, and Derating........................................................................................... 91 Data Setup, Hold, and Derating....................................................................................................................... 99 Commands - Truth Tables............................................................................................................................. 108 Commands................................................................................................................................................... 111 DESELECT................................................................................................................................................ 111 NO OPERATION........................................................................................................................................ 111 ZQ CALIBRATION LONG........................................................................................................................... 111 ZQ CALIBRATION SHORT.......................................................................................................................... 111 ACTIVATE................................................................................................................................................. 111 READ........................................................................................................................................................ 111 WRITE...................................................................................................................................................... 112 PRECHARGE............................................................................................................................................. 113 REFRESH.................................................................................................................................................. 113 SELF REFRESH.......................................................................................................................................... 114 DLL Disable Mode..................................................................................................................................... 115 Input Clock Frequency Change...................................................................................................................... 119 Write Leveling............................................................................................................................................... 121 Write Leveling Procedure........................................................................................................................... 123 Write Leveling Mode Exit Procedure........................................................................................................... 125
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Specifications: Memory Type: DDR3 SDRAM ; Memory Size: 4G (512M x 8) ; Speed: 667MH Interface: Parallel (Byte-wide) ; Package / Case: 78-TFBGA ; Packaging: B Voltage - Supply: 1.425 V ~ 1.575 V ; Operating
Specifications: Memory Type: DDR3 SDRAM ; Memory Size: 1G (64M x 16) ; Speed: 800MH Interface: Parallel (Byte-wide) ; Package / Case: 96-TFBGA ; Packaging: B Voltage - Supply: 1.425 V ~ 1.575 V ; Operating
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