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一种基于双天线的北斗定位系统设计与实现
[导读] 前期实际北斗模块定位误差统计分析中得出了北斗模块的定位误差分布服从正态分布，根据北斗模块定位误差分布的规律，利用在同一块电路板上的双天线模块接收北斗定位信号，将定位信息传给TMS320F28335DSP芯片，DSP对北斗模块给出的定位信息做实时算法处理，并将处理后的定位信息传给嵌入式ARM芯片，ARM芯片在TFT液晶屏上更新定位信息，同时根据用户要求来设置北斗模块的工作模式。在接收不到北斗定位信息时DSP利用UKF滤波算法，将预测定位信息发送给ARM芯片，并标记为预测信息，且显示在TFT液晶屏上。
是我国自主开发的，目前在轨运行卫星已达16颗，截止日，我国的空间信号接口控制文件正式版已公布，北斗定位导航业务正式对亚太地区提供无源定位、导航及授时服务。该系统可为汽车、客机和轮船等常用交通工具提供定位服务，为精确制导武器提供定位导航服务，其对我国军事国防事业摆脱对国外系统依赖有着重要意义，另外对农牧业、渔业生产也有着重要意义。
在众多实际应用背景下，如何提高卫星定位导航系统的定位精度就显得尤为重要。本文提出一种基于双天线结构的构想，以提高北斗定位模块的定位精度为目的，在ARM+DSP系统上实现。
1 系统设计思想
在卫星定位系统众多应用中，常用于描述卫星定位精度的参数主要有水乎均方根误差(Distance Root-Mean-Square，DRMS)、圆概率误差(Circular Error Probable，CEP)和球概率误差(Spherical Error Probable，SEP)等，这些参数被广泛用于测量和各种定位系统中，其计算和准确性与定位误差的三维分布特征密切相关。文献证明在一般情况下，定位误差的三维分布呈椭球状，被称为误差椭球。其几何特征主要包括椭球的轴方向、轴长和轴比。轴方向是椭球的3个主轴所在的方向，轴长是定位误差在椭球轴方向上的标准差，轴比是椭球3个轴长之间的比值。误差椭球的轴比决定了真实位置落在DRMS圆上的概率。
在对文献分析后，进行单点100组连续北斗模块定位测试，统计误差分布规律，经实际测试、统计分析得出北斗模块的实际定位误差近似服从正态分布，北斗定位模块的水平定位误差依91%的概率收敛于8～10 m之间，其中9 m处的分布概率为82%，如图1所示。
图1 北斗模块测试统计情况
DRMS值为9.0 m，记作R，在实际测量中北斗模块给出一组定位数据(a1，b1)，记作A，a1、b1分别表示经度和纬度信息，则以(a1，b1)为圆心的DRMS圆如图2所示。
图2 北斗定位二维DRMS圆示意图
在同一块电路板上使用双天线模块接收北斗定位导航信息，由于将两个天线并排安放，所以在任意时刻两个北斗定位模块相对于的通信链路相同，两个北斗定位模块可见星情况和接收到的前端卫星定位信息也相同。假定某一时刻两个模块接收到的定位信息分别为(a1，b1)和(a2，b2)，以(a1，b1)和(a2，b2)为圆心，R为半径的DRMS圆，两圆记为A、B，则真实点依大概率收敛于两个圆交点中(a3，b3)、(a4，b4)。根据前一时刻的位置信息和速度信息可排除其中一个交点(a3，b3)或(a4，b4)，则剩下的点就为真实位置的最大概率分布点。
图3 北斗双天线真实点分布示意图
2 系统硬件设计
系统使用DSP+ARM双结构，DSP主要负责接收北斗模块的定位信息和算法处理功能，ARM负责与DSP通信、控制TFT液晶屏的显示功能。硬件设计主要包括电源部分、ARM部分、DSP部分、网络部分、TFT液晶屏部分以及北斗模块多部分的设计。
2.1 系统硬件结构框图
图4 系统硬件框图
2.2 电源部分
系统使用较为常见的12 V电压作为总的电源输入，经LM2596得到5 V电压作为DSP模块和TFT液晶屏的电源，5 V电压经ASM1117得到3.3 V电压作为ARM模块和网络部分以及TF卡的电源。
2.3 ARM部分设计
ARM使用意法半导体公司的STM32F103VET6，该为32位Cortex&M3内核微处理器，主频最高可达72 MHz，封装为LQFP100，减小了PCB板的面积。另外，还支持IO管脚的重映射配置，降低了PCB布线的难度，且支持JTAG、SWD两种调试/下载模式，方便用户使用市面上较为常见的调试工具J-LINK调试/下载程序，因此使用方便。
2.4 DSP部分说明
DSP部分使用的为TI公司的新型数字信号处理器TMS320F28335，该款最高主频达150 MHz，采用哈佛流水线结构，并具有片内硬件乘法器，完成一次浮点数的乘加运算只需10个机器周期，故可进行高速数据运算。
2.5 网络部分说明
网络部分主要提供了一个可选功能，当条件满足时可将系统的定位信息发送到上，供远端的用户访问、查询。
系统使用美国微星公司的ENC28J60网络，该为IEEE802.3兼容的以太网，支持全/半双工模式，工作电压兼容TTL电平和CMOS电平，可编程会在发生冲突时自动重发，可编程填充和CRC生成，用于快速发送数据的内部FIFO、DMA以及硬件支持的IP校验和计算。其封装为SSOP28，与微处理器的链接方式为SPI总线，因此控制方便，最高速度可达10 Mbit&s-1。
2.6 TFT液晶屏部分说明
TFT液晶屏的每个像点均是由集成在像素点后面的薄膜晶体管来驱动的，从而可做到高速度、高亮度、高对比度显示屏幕信息，是目前最佳的LCD彩色显示设备之一，其效果接近CRT显示器，是现在笔记本电脑和台式机上的主流显示设备。
系统使用16 bit真彩色，320&240分辨率TFT液晶屏。STM32F103ARM负责TFT液晶屏的驱动，STM32F103ARM与TFT液晶屏之间使用FSMC总线通信，以完成对该液晶屏的初始化和显示控制。
2.7 北斗模块部分说明
北斗模块部分使用北京和芯星通公司的UM220北斗定位，其可同时支持BD2 B1、GPS L1两个频点，输出数据方式为USART，数据协议为NMEA 0183，默认通信波特率为9 600 bit&s-1，并可根据用户需要自行设定最高支持波特率为230 400 bit&s-1，其输入/输出信号类型均为LVTTL电平。
UM220通过串口与DSP连接，DSP通过串口完成对北斗模块的配置，并接收其定位信息。
3 系统工作流程
3.1 系统总体工作流程
系统采用DSP+ARM双核结构，DSP与ARM各司其职。在系统上电后，DSP、ARM完成上电复位，DSP通过USART接收北斗定位模块的定位信息，在不失星的情况下进行北斗双天线定位算法计算。而DSP在进行北斗双天线定位算法计算后，通过串口将计算后的北斗定位信息发送给ARM。若处于失星的情况下，进行UKF算法轨迹预测，并将得到的预测结果通过串口发送给ARM，ARM接收到北斗定位信息后，通过FSMC总线将定位信息更新到TFT液晶屏上，如图5所示。
图5 系统程序流程图
3.2 轨迹预测算法设计
系统采用无迹卡尔曼滤波(UKF)做为失星情况下的轨迹预测算法。无迹卡尔曼滤波(UKF)是一种基于最小方差估计准则的非线性状态估计器，其以非线性最优高斯作为基本理论框架。UKF采用UT变换技术，即采用确定的样本点(Sigma点)来完成状态变量统计特性沿时间的传播，改进了扩展卡尔曼滤波(EKF)不能求解雅可比矩阵以及泰勒级数线性化只具有一阶的低精度问题，其逼近精度可达二阶或二阶以上。U KF算法实现过程如下
式中，x为未失星前时刻北斗双天线定位所得定位经、纬度信息;px是x的协方差;n表示系统状态维数;北斗应用中n取值为2;&是微调参数，其可控制样本点到均值的距离。
step2 根据系统状态方程求样本点传递值
Step3 求系统定位误差均值和方差的一步预测
Step4 根据系统量测方程求取定位误差状态一步预测的传递值
Step5 获得定位误差均值和协方差
式中，pzz是定位误差的量测方差矩阵;pxz是定位误差状态向量与定位误差量测向量的协方差矩阵。
Step6 计算UKF增益，更新定位误差状态向量和方差
4 系统测试
4.1 北斗双天线定位测试
该测试需对北斗双天线定位思想设计进行验证，对系统的定位精度进行实际测试。在晴天的情况下，单北斗模块定位精度约在9 m，双天线北斗模块定位精度约为3.3 m，GPS的定位精度约在10 m，这说明使用双天线结构大幅提升了北斗定位模块的定位精度，如表1所示。
表1 北斗双天线测试数据对比
4.2 轨迹预测测试
轨迹预测测试选定在晴天情况下，首先沿固定路线运动，然后重新沿固定路线运动，在特定时刻经北斗双天线定位模块的天线取下，然后对比路线轨迹与轨迹预测算法得到的轨迹数据。如图6所示。
图6 轨迹预测算法实际测试
图中横轴坐标为经度坐标，标定到&分&，均为东经126&xx分，xx为图中横轴标定坐标值;纵轴坐标为纬度坐标，标定到&分&，均为北纬45&xx分，xx为图中纵坐标值。实线轨迹data1为在谷歌地图上标定的真实运动路线，星点状轨迹data2为得到实际运动路线后，精确到重新测定运动轨迹失星时刻前后的运动路线。两次轨迹对比结果表明，在失星情况下采用UKF算法所进行轨迹预测得到临近时刻定位数据的定位精度大约在10 m，介于单模块北斗定位精度和GPS定位精度之间，但随着失星时间的增长，轨迹预测的误差将会增大，在20个采样点后，轨迹预测得到数据的误差将增大至50 m以上。
定位精度是本系统的关键，经实际测试在晴天的情况下北斗双天线定位思想设计可大幅度提高北斗定位模块的定位精度。而在其他的定位系统上，若两个定位模块精度相差较小时，也可应用双天线定位思想，提高系统的定位精度。
此外，系统还可使用性能更好的嵌入式处理器，如TI的DM37XX系列，内嵌有&DSP+ARM&双核，既可以做复杂运算，也可进行复杂控制，这样便可减小系统的体积与使用数量，从而简化系统设计，使系统更加便于使用。
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TI公司 tms320f28335 DSP用户手册
TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232Digital Signal Controllers (DSCs)Data ManualPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Literature Number: SPRS439G June 2007 C Revised February 2010TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.comContents1 TMS320F2833x, TMS320F2823x DSCs234.................................................................................. 1.1 Features .................................................................................................................... 1.2 Getting Started ............................................................................................................. Introduction ...................................................................................................................... 2.1 Pin Assignments ........................................................................................................... 2.2 Signal Descriptions ........................................................................................................ Functional Overview .......................................................................................................... 3.1 Memory Maps .............................................................................................................. 3.2 Brief Descriptions .......................................................................................................... 3.2.1 C28x CPU ....................................................................................................... 3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 3.2.3 Peripheral Bus .................................................................................................. 3.2.4 Real-Time JTAG and Analysis ................................................................................ 3.2.5 External Interface (XINTF) .................................................................................... 3.2.6 Flash ............................................................................................................. 3.2.7 M0, M1 SARAMs ............................................................................................... 3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 3.2.9 Boot ROM ....................................................................................................... 3.2.10 Security .......................................................................................................... 3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 3.2.12 External Interrupts (XINT1CXINT7, XNMI) .................................................................. 3.2.13 Oscillator and PLL .............................................................................................. 3.2.14 Watchdog ........................................................................................................ 3.2.15 Peripheral Clocking ............................................................................................. 3.2.16 Low-Power Modes .............................................................................................. 3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 3.2.20 Control Peripherals ............................................................................................. 3.2.21 Serial Port Peripherals ......................................................................................... 3.3 Register Map ............................................................................................................... 3.4 Device Emulation Registers .............................................................................................. 3.5 Interrupts .................................................................................................................... 3.5.1 External Interrupts .............................................................................................. 3.6 System Control ............................................................................................................ 3.6.1 OSC and PLL Block ............................................................................................ 3.6.1.1 External Reference Oscillator Clock Option .................................................... 3.6.1.2 PLL-Based Clock Module ......................................................................... 3.6.1.3 Loss of Input Clock ................................................................................ 3.6.2 Watchdog Block ................................................................................................. 3.7 Low-Power Modes Block ................................................................................................. Peripherals ....................................................................................................................... 4.1 DMA Overview ............................................................................................................. 4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 ) ........................................................................Contents1111 121315 243435 42 42 42 42 43 43 43 43 44 44 44 46 46 46 46 46 46 47 47 47 48 48 49 51 52 56 57 58 59 60 61 62 636464 66 682Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 201056....................................................................................... 72 ........................................................................... 73 4.6 Enhanced QEP Modules (eQEP1/2 ) ................................................................................... 75 4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 77 4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 81 4.7.2 ADC Registers .................................................................................................. 82 4.7.3 ADC Calibration ................................................................................................. 83 4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 84 4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 87 4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 92 4.11 Serial Peripheral Interface (SPI) Module (SPI-A ) ..................................................................... 96 4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 99 4.13 GPIO MUX ................................................................................................................ 100 4.14 External Interface (XINTF) .............................................................................................. 107 Device Support ................................................................................................................ 109 5.1 Device and Development Support Tool Nomenclature ............................................................. 109 5.2 Documentation Support ................................................................................................. 111 Electrical Specifications ................................................................................................... 116 6.1 Absolute Maximum Ratings ............................................................................................. 116 6.2 Recommended Operating Conditions ................................................................................. 117 6.3 Electrical Characteristics ................................................................................................ 117 6.4 Current Consumption .................................................................................................... 118 6.4.1 Reducing Current Consumption ............................................................................. 120 6.4.2 Current Consumption Graphs ............................................................................... 121 6.4.3 Thermal Design Considerations ............................................................................. 122 6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 123 6.6 Timing Parameter Symbology .......................................................................................... 124 6.6.1 General Notes on Timing Parameters ...................................................................... 124 6.6.2 Test Load Circuit .............................................................................................. 124 6.6.3 Device Clock Table ........................................................................................... 125 6.7 Clock Requirements and Characteristics ............................................................................. 126 6.8 Power Sequencing ....................................................................................................... 127 6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 127 6.9 General-Purpose Input/Output (GPIO) ................................................................................ 130 6.9.1 GPIO - Output Timing ........................................................................................ 130 6.9.2 GPIO - Input Timing .......................................................................................... 131 6.9.3 Sampling Window Width for Input Signals ................................................................. 132 6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 133 6.10 Enhanced Control Peripherals ......................................................................................... 138 6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 138 6.10.2 Trip-Zone Input Timing ....................................................................................... 138 6.10.3 Enhanced Capture (eCAP) Timing ......................................................................... 139 6.10.4 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 139 6.10.5 ADC Start-of-Conversion Timing ............................................................................ 140 6.11 External Interrupt Timing ................................................................................................ 140 6.12 I2C Electrical Specification and Timing ............................................................................... 141 6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 1414.4 4.5 High-Resolution PWM (HRPWM) Enhanced CAP Modules (eCAP1/2/3/4/5/6)Contents 3Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.com6.13.1 6.14Master Mode Timing..........................................................................................1416.13.2 SPI Slave Mode Timing ...................................................................................... 146 External Interface (XINTF) Timing ..................................................................................... 149 6.14.1 USEREADY = 07 8............................................................................................... 149 6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 150 6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 151 6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 153 6.14.5 External Interface Read Timing ............................................................................. 154 6.14.6 External Interface Write Timing ............................................................................. 156 6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 158 6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 161 6.14.9 XHOLD and XHOLDA Timing ............................................................................... 164 6.15 On-Chip Analog-to-Digital Converter .................................................................................. 167 6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 168 6.15.2 Definitions ...................................................................................................... 169 6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 170 6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 171 6.15.5 Detailed Descriptions ......................................................................................... 172 6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 173 6.16.1 McBSP Transmit and Receive Timing ...................................................................... 173 6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 176 6.17 Flash Timing .............................................................................................................. 180 6.18 Migrating Between F2833x Devices and F2823x Devices ......................................................... 181 Revision History .............................................................................................................. 182 Thermal/Mechanical Data .................................................................................................. 1854ContentsCopyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010List of Figures2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 5-1 6-1 F2833x, F-Pin PGF/PTP LQFP (Top View) ...................................................................... 15 F2833x, F-Ball ZHH MicroStar BGA? (Upper Left Quadrant) (Bottom View) F2833x, F-Ball ZHH MicroStar BGA? (Lower Left Quadrant) (Bottom View).............................. ..............................17 19F2833x, F-Ball ZHH MicroStar BGA? (Upper Right Quadrant) (Bottom View) ............................. 18 F2833x, F-Ball ZHH MicroStar BGA ?(Lower Right Quadrant) (Bottom View) ............................. 20 F2833x, F-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View) ...................................... 21 F2833x, F-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View) .................................... 22 F2833x, F-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View) ...................................... 23 F2833x, F-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View) .................................... 23...................................................................................................... ................................................................................................. F2 Memory Map ................................................................................................. F2 Memory Map ................................................................................................. External and PIE Interrupt Sources ............................................................................................ External Interrupts ................................................................................................................ Multiplexing of Interrupts Using the PIE Block ............................................................................... Clock and Reset Domains ...................................................................................................... OSC and PLL Block Diagram................................................................................................... Using a 3.3-V External Oscillator............................................................................................... Using a 1.9 -V External Oscillator .............................................................................................. Using the Internal Oscillator .................................................................................................... Watchdog Module ................................................................................................................ DMA Functional Block Diagram ................................................................................................ CPU-Timers ....................................................................................................................... CPU-Timer Interrupt Signals and Output Signal ............................................................................. Multiple PWM Modules in an x System ......................................................................... ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... eCAP Functional Block Diagram ............................................................................................... eQEP Functional Block Diagram ............................................................................................... Block Diagram of the ADC Module ............................................................................................ ADC Pin Connections With Internal Reference .............................................................................. ADC Pin Connections With External Reference ............................................................................. McBSP Module .................................................................................................................. eCAN Block Diagram and Interface Circuit ................................................................................... eCAN-A Memory Map ........................................................................................................... eCAN-B Memory Map ........................................................................................................... Serial Communications Interface (SCI) Module Block Diagram............................................................ SPI Module Block Diagram (Slave Mode) .................................................................................... I2C Peripheral Module Interfaces .............................................................................................. GPIO MUX Block Diagram .................................................................................................... Qualification Using Sampling Window ....................................................................................... External Interface Block Diagram ............................................................................................. Typical 16-bit Data Bus XINTF Connections ................................................................................ Typical 32-bit Data Bus XINTF Connections ................................................................................ Example of F2833x, F2823x Device Nomenclature ........................................................................ Typical Operational Current Versus Frequency (F2/F2) ...................................Functional Block Diagram F2 Memory MapList of Figures34 37 38 39 53 53 54 57 58 59 59 59 62 65 66 66 68 71 73 75 78 79 80 85 88 89 90 95 98 99 101 106 107 108 108 110 1225Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.com6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40Typical Operational Power Versus Frequency (F2/F2) .................................... 122 Emulator Connection Without Signal Buffering for the DSP.............................................................1233.3-V Test Load Circuit......................................................................................................... 124 Clock Timing ..................................................................................................................... 127 Power-on Reset ................................................................................................................. 128 Warm Reset ..................................................................................................................... 129 Example of Effect of Writing Into PLLCR Register ......................................................................... 130 General-Purpose Output Timing .............................................................................................. 131 Sampling Mode.................................................................................................................131General-Purpose Input Timing ................................................................................................ 132 IDLE Entry and Exit Timing .................................................................................................... 133 STANDBY Entry and Exit Timing Diagram .................................................................................. 135 HALT Wake-Up Using GPIOn................................................................................................. 137 PWM Hi-Z Characteristics ..................................................................................................... 138 ADCSOCAO or ADCSOCBO Timing........................................................................................140External Interrupt Timing ....................................................................................................... 140 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 143 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 145 SPI Slave Mode External Timing (Clock Phase = 0) ....................................................................... 147 SPI Slave Mode External Timing (Clock Phase = 1) ....................................................................... 148 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 152 Example Read Access ......................................................................................................... 155 Example Write Access ......................................................................................................... 157 Example Read With Synchronous XREADY Access......................................................................159Example Read With Asynchronous XREADY Access ..................................................................... 160 Write With Synchronous XREADY Access .................................................................................. 162 Write With Asynchronous XREADY Access................................................................................163External Interface Hold Waveform ............................................................................................ 165 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................. 166 ADC Power-Up Control Bit Timing...........................................................................................168ADC Analog Input Impedance Model ........................................................................................ 169 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 170....................................................................................... McBSP Receive Timing ........................................................................................................ McBSP Transmit Timing ....................................................................................................... McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ...................................................Simultaneous Sampling Mode Timing171 175 175 176 177 178 1796List of FiguresCopyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010List of Tables2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 5-1 6-1 6-2 6-3 6-4.................................................................................................... 13 F2823x Hardware Features .................................................................................................... 14 Signal Descriptions ............................................................................................................... 24 Addresses of Flash Sectors in F2 ............................................................................. 39 Addresses of Flash Sectors in F2 .............................................................................. 39 Addresses of Flash Sectors in F2 .............................................................................. 39 Handling Security Code Locations ............................................................................................. 40 Wait-states ........................................................................................................................ 41 Boot Mode Selection ............................................................................................................. 44 Peripheral Frame 0 Registers .................................................................................................. 49 Peripheral Frame 1 Registers .................................................................................................. 49 Peripheral Frame 2 Registers .................................................................................................. 50 Peripheral Frame 3 Registers .................................................................................................. 50 Device Emulation Registers..................................................................................................... 51 PIE Peripheral Interrupts ....................................................................................................... 54 PIE Configuration and Control Registers...................................................................................... 55 External Interrupt Registers ..................................................................................................... 56 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 58 PLL Settings ...................................................................................................................... 60 CLKIN Divide Options ........................................................................................................... 60 Possible PLL Configuration Modes ............................................................................................ 61 Low-Power Modes ............................................................................................................... 63 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 67 ePWM Control and Status Registers (Default Configuration in PF1)...................................................... 69 ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible) ........................... 70 eCAP Control and Status Registers ........................................................................................... 74 eQEP Control and Status Registers ........................................................................................... 76 ADC Registers ................................................................................................................... 82 McBSP Register Summary ...................................................................................................... 86 3.3-V eCAN Transceivers ...................................................................................................... 88 CAN Register Map .............................................................................................................. 91 SCI-A Registers .................................................................................................................. 93 SCI-B Registers .................................................................................................................. 93 SCI-C Registers ................................................................................................................. 94 SPI-A Registers................................................................................................................... 97 I2C-A Registers ................................................................................................................. 100 GPIO Registers ................................................................................................................. 102 GPIO-A Mux Peripheral Selection Matrix ................................................................................... 103 GPIO-B Mux Peripheral Selection Matrix ................................................................................... 104 GPIO-C Mux Peripheral Selection Matrix ................................................................................... 105 XINTF Configuration and Control Register Mapping ....................................................................... 108 TMS320x2833x, 2823x Peripheral Selection Guide ....................................................................... 111 TMS320F2 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 118 TMS320F2 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 119 Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 120 Clocking and Nomenclature (150-MHz Devices) ........................................................................... 125F2833x Hardware FeaturesList of Tables 7Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.com6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 6-51 6-528Clocking and Nomenclature (100-MHz Devices) ........................................................................... 125 Input Clock Frequency ......................................................................................................... 126............................................................................. XCLKIN Timing Requirements C PLL Disabled ............................................................................ XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... Power Management and Supervisory Circuit Solutions ................................................................... Reset (XRS) Timing Requirements .......................................................................................... General-Purpose Output Switching Characteristics ........................................................................ General-Purpose Input Timing Requirements .............................................................................. IDLE Mode Timing Requirements ........................................................................................... IDLE Mode Switching Characteristics ....................................................................................... STANDBY Mode Timing Requirements ..................................................................................... STANDBY Mode Switching Characteristics ................................................................................ HALT Mode Timing Requirements ........................................................................................... HALT Mode Switching Characteristics ...................................................................................... ePWM Timing Requirements ................................................................................................. ePWM Switching Characteristics ............................................................................................ Trip-Zone Input Timing Requirements ...................................................................................... High-Resolution PWM Characteristics at SYSCLKOUT = (60 C150 MHz) .............................................. Enhanced Capture (eCAP) Timing Requirement .......................................................................... eCAP Switching Characteristics ............................................................................................. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. eQEP Switching Characteristics ............................................................................................. External ADC Start-of-Conversion Switching Characteristics ............................................................. External Interrupt Timing Requirements .................................................................................... External Interrupt Switching Characteristics ................................................................................ I2C Timing ...................................................................................................................... SPI Master Mode External Timing (Clock Phase = 0) .................................................................... SPI Master Mode External Timing (Clock Phase = 1) .................................................................... SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... XINTF Clock Configurations .................................................................................................. External Interface Read Timing Requirements ............................................................................. External Interface Read Switching Characteristics ......................................................................... External Interface Write Switching Characteristics ......................................................................... External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ................................... External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. ADC Electrical Characteristics (over recommended operating conditions) ............................................ ADC Power-Up Delays ......................................................................................................... Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ..............................XCLKIN Timing Requirements C PLL EnabledList of Tables126 126 126 127 129 130 131 133 133 134 134 136 136 138 138 138 139 139 139 139 139 140 140 140 141 142 144 146 148 149 152 154 154 156 158 158 158 158 161 161 161 165 166 167 168 168Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 20106-53 6-54 6-55 6-56 6-57 6-58 6-59 6-60 6-61 6-62 6-63 6-64 6-65 6-66 6-67 6-68 6-69 8-1 8-2 8-3 8-4Sequential Sampling Mode Timing ........................................................................................... 170....................................................................................... ................................................................................................ McBSP Switching Characteristics ........................................................................................... McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ............................ McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ............................ McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ............................ McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... Flash Endurance for A and S Temperature Material ...................................................................... Flash Endurance for Q Temperature Material .............................................................................. Flash Parameters at 150-MHz SYSCLKOUT ............................................................................... Flash/OTP Access Timing ..................................................................................................... Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... Thermal Model 176-Pin PGF Results ........................................................................................ Thermal Model 176-Pin PTP Results ........................................................................................ Thermal Model 179-Ball ZHH Results ....................................................................................... Thermal Model 176-Ball ZJZ Results .......................................................................................Simultaneous Sampling Mode Timing McBSP Timing Requirements171 173 174 176 176 177 177 178 178 179 179 180 180 180 180 180 185 185 185 186Copyright ? , Texas Instruments IncorporatedList of Tables9TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.com10List of TablesCopyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010Digital Signal Controllers (DSCs)Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F2823211.1123TMS320F2833x, TMS320F2823x DSCsFeatures? Enhanced Control Peripherals C Up to 18 PWM Outputs C Up to 6 HRPWM Outputs With 150 ps MEP Resolution C Up to 6 Event Capture Inputs C Up to 2 Quadrature Encoder Interfaces C Up to 8 32-Bit/Nine 16-Bit Timers ? Three 32-Bit CPU Timers ? Serial Port Peripherals C Up to 2 CAN Modules C Up to 3 SCI (UART) Modules C Up to 2 McBSP Modules (Configurable as SPI) C One SPI Module C One Inter-Integrated-Circuit (I2C) Bus ? 12-Bit ADC, 16 Channels C 80-ns Conversion Rate C 2 x 8 Channel Input Multiplexer C Two Sample-and-Hold C Single/Simultaneous Conversions C Internal or External Reference ? Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering ? JTAG Boundary Scan Support (1) ? Advanced Emulation Features C Analysis and Breakpoint Functions C Real-Time Debug via Hardware ? Development Support Includes C ANSI C/C++ Compiler/Assembler/Linker C Code Composer Studio? IDE C DSP/BIOS? C Digital Motor Control and Digital Power Software Libraries ? Low-Power Modes and Power Savings C IDLE, STANDBY, HALT Modes Supported C Disable Individual Peripheral Clocks? High-Performance Static CMOS Technology C Up to 150 MHz (6.67-ns Cycle Time) C 1.9-V/1.8 -V Core, 3.3-V I/O Design ? High-Performance 32-Bit CPU (TMS320C28x) C IEEE-754 Single-Precision Floating-Point Unit (FPU) (F2833x only) C 16 x 16 and 32 x 32 MAC Operations C 16 x 16 Dual MAC C Harvard Bus Architecture C Fast Interrupt Response and Processing C Unified Memory Programming Model C Code-Efficient (in C/C++ and Assembly) ? Six-Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM) ? 16-Bit or 32-Bit External Interface (XINTF) C Over 2M x 16 Address Reach ? On-Chip Memory C F2: 256K x 16 Flash, 34K x 16 SARAM C F2: 128K x 16 Flash, 34K x 16 SARAM C F2: 64K x 16 Flash, 26K x 16 SARAM C 1K x 16 OTP ROM ? Boot ROM (8K x 16) C With Software Boot Modes (via SCI, SPI, CAN, I2C, McBSP, XINTF, and Parallel I/O) C Standard Math Tables ? Clock and System Control C Dynamic PLL Ratio Changes Supported C On-Chip Oscillator C Watchdog Timer Module ? GPIO0 to GPIO63 Pins Can Be Connected to One of the Eight External Core Interrupts ? Peripheral Interrupt Expansion (PIE) Block That Supports All 58 Peripheral Interrupts ? 128-Bit Security Key/Lock C Protects Flash/OTP/RAM Blocks C Prevents Firmware Reverse Engineering1(1)IEEE Standard 0 Standard Test Access Port and Boundary Scan ArchitecturePlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar BGA, Code Composer Studio, DSP/BIOS, TMS320C28x, Delfino, PowerPAD, TMS320C54x, TMS320C55x, C28x are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.2 3PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.com? Package Options: C Lead-free, Green Packaging C Low-Profile Quad Flatpack (PGF, PTP) C MicroStar BGA? (ZHH) C Plastic BGA (ZJZ)? Temperature Options: C A: C40°C to 85°C (PGF, ZHH, ZJZ) C S: C40°C to 125°C (PTP, ZJZ) C Q: C40°C to 125°C (PTP, ZJZ) ? Community Resources C TI E2E Community C TI Embedded Processors Wiki1.2Getting StartedThis section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: ? Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). ? C2000 Getting Started Website (http://www.ti.com/c2000getstarted) ? TMS320F28x DSC Development and Experimenter's Kits (http://www.ti.com/f28xkits)12TMS320F2833x, TMS320F2823x DSCsCopyright ? , Texas Instruments IncorporatedSubmit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 20102IntroductionThe TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x?/ Delfino? DSC/MCU generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as F28335, F28334, F28332, F28235, F28234, and F28232, respectively. Table 2-1 and Table 2-2 provide a summary of features for each device. Table 2-1. F2833x Hardware FeaturesFEATURE TYPE (1) C C C C C C C 1 0 0 0 0 0 C No. of channels MSPS Conversion time 2 C 1 0 0 0 0 C C 176-Pin PGF C C C C C C C 176-Pin PTP 179-Ball ZHH 176-Ball ZJZ A: C40°C to 85°C F2 MHz) 6.67 ns Yes 256K 34K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A/5A/6A eCAP1/2/3/4/5/6 eQEP1/2 Yes 16 12.5 80 ns 3 2 (A/B) 1 3 (A/B/C) 2 (A/B) 1 88 8 Yes Yes Yes Yes (PGF, ZHH, ZJZ) (PTP, ZJZ) (PTP, ZJZ) F2 MHz) 6.67 ns Yes 128K 34K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A/5A/ 6A eCAP1/2/3/4 eQEP1/2 Yes 16 12.5 80 ns 3 2 (A/B) 1 3 (A/B/C) 2 (A/B) 1 88 8 Yes No Yes Yes (PGF, ZHH, ZJZ) (ZJZ) (ZJZ) F2 MHz) 10 ns Yes 64K 26K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A eCAP1/2/3/4 eQEP1/2 Yes 16 12.5 80 ns 3 1 (A) 1 2 (A/B) 2 (A/B) 1 88 8 Yes No Yes Yes (PGF, ZHH, ZJZ) (ZJZ) (ZJZ)Instruction cycle Floating-point Unit 3.3-V on-chip flash (16-bit word) Single-access RAM (SARAM) (16-bit word) One-time programmable (OTP) ROM (16-bit word) Code security for on-chip flash/SARAM/OTP blocks Boot ROM (8K x 16) 16/32-bit External Interface (XINTF) 6-channel Direct Memory Access (DMA) PWM outputs HRPWM channels 32-bit Capture inputs or auxiliary PWM outputs 32-bit QEP channels (four inputs/channel) Watchdog timer 12-Bit ADC 32-Bit CPU timers Multichannel Buffered Serial Port (McBSP)/SPI Serial Peripheral Interface (SPI) Serial Communications Interface (SCI) Enhanced Controller Area Network (eCAN) Inter-Integrated Circuit (I2C) General Purpose I/O pins (shared) External interruptsPackagingTemperature optionsS: C40°C to 125°C Q: C40°C to 125°C (Q100 Qualification)(1)A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. Introduction Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 13Copyright ? , Texas Instruments IncorporatedTMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232SPRS439G C JUNE 2007 C REVISED FEBRUARY 2010 www.ti.comTable 2-1. F2833x Hardware Features (continued)FEATURE Product status (2)(2)TYPE (1) CF2 MHz) TMSF2 MHz) TMSF2 MHz) TMSSee Section 5.1 , Device and Development Support Tool Nomenclature, for descriptions of device stages.Table 2-2. F2823x Hardware FeaturesFEATURE Instruction cycle Floating-point Unit 3.3-V on-chip flash (16-bit word) Single-access RAM (SARAM) (16-bit word) One-time programmable (OTP) ROM (16-bit word) Code security for on-chip flash/SARAM/OTP blocks Boot ROM (8K x 16) 16/32-bit External Interface (XINTF) 6-channel Direct Memory Access (DMA) PWM outputs HRPWM channels 32-bit Capture inputs or auxiliary PWM outputs 32-bit QEP channels (four inputs/channel) Watchdog timer No. of channels 12-Bit ADC 32-Bit CPU timers Multichannel Buffered Serial Port (McBSP)/SPI Serial Peripheral Interface (SPI) Serial Communications Interface (SCI) Enhanced Controller Area Network (eCAN) Inter-Integrated Circuit (I2C) General Purpose I/O pins (shared) External interrupts 176-Pin PGF Packaging 176-Pin PTP 179-Ball ZHH 176-Ball ZJZ A: C40°C to 85°C S: C40°C to 125°C Temperature options Q: C40°C to 125°C (Q100 Qualification) MSPS Conversion time C 1 0 0 0 0 C C C C C C C C C C 2 TYPE (1) C C C C C C C 1 0 0 0 0 0 C F2 MHz) 6.67 ns No 256K 34K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A/5A/6A eCAP1/2/3/4/5/6 eQEP1/2 Yes 16 12.5 80 ns 3 2 (A/B) 1 3 (A/B/C) 2 (A/B) 1 88 8 Yes Yes Yes Yes (PGF, ZHH, ZJZ) (PTP, ZJZ) (PTP, ZJZ) TMS F2 MHz) 6.67 ns No 128K 34K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A/5A/6A eCAP1/2/3/4 eQEP1/2 Yes 16 12.5 80 ns 3 2 (A/B) 1 3 (A/B/C) 2 (A/B) 1 88 8 Yes No Yes Yes (PGF, ZHH, ZJZ) (ZJZ) (ZJZ) TMS F2 MHz) 10 ns No 64K 26K 1K Yes Yes Yes Yes ePWM1/2/3/4/5/6 ePWM1A/2A/3A/4A eCAP1/2/3/4 eQEP1/2 Yes 16 12.5 80 ns 3 1 (A) 1 2 (A/B) 2 (A/B) 1 88 8 Yes No Yes Yes (PGF, ZHH, ZJZ) (ZJZ) (ZJZ) TMSProduct status (2) (1) (2)A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. See Section 5.1 , Device and Development Support Tool Nomenclature, for descriptions of device stages.14IntroductionCopyright ? , Texas Instruments IncorporatedSubmit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232www.ti.com SPRS439G C JUNE 2007 C REVISED FEBRUARY 20102.1Pin AssignmentsThe 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1. The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5. The 176-ball ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through Figure 2-9.Table 2-3 describes the function(s) of each pin.GPIO75/XD4 GPIO74/XD5 GPIO73/XD6 GPIO72/XD7 GPIO71/XD8 GPIO70/XD9 VDD VSS GPIO69/XD10 GPIO68/XD11 GPIO67/XD12 VDDIO VSS GPIO66/XD13 VSS VDD GPIO65/XD14 GPIO64/XD15 GPIO63/SCITXDC/XD16 GPIO62/SCIRXDC/XD17 GPIO61/MFSRB/XD18 GPIO60/MCLKRB/XD19 GPIO59/MFSRA/XD20 VDD VSS VDDIO VSS XCLKIN X1 VSS X2 VDD GPIO58/MCLKRA/XD21 GPIO57/SPISTEA/XD22 GPIO56/SPICLKA/XD23 GPIO55/SPISOMIA/XD24 GPIO54/SPISIMOA/XD25 GPIO53/EQEP1I/XD26 GPIO52/EQEP1S/XD27 VDDIO VSS GPIO51/EQEP1B/XD28 GPIO50/EQEP1A/XD29 GPIO49/ECAP6/XD30GPIO76/XD3 GPIO77/XD2 GPIO78/XD1 GPIO79/XD0 GPIO38/XWE0 XCLKOUT VDD GPIO28/SCIRXDA/XZCS6 VSS GPIO28/SCIRXDA/XZCS6 GPIO34/ECAP1/XREADY VDDIO VSS GPIO36/SCIRXDA/XZCS0 VDD VSS GPIO35/SCITXDA/XR/W XRD GPIO37/ECAP2/XZCS7 GPIO40/XA0/XWE1 GPIO41/XA1 GPIO42/XA2 VDD VSS GPIO43/XA3 GPIO44/XA4 GPIO45/XA5 VDDIO VSS GPIO46/XA6 GPIO47/XA7 GPIO80/XA8 GPIO81/XA9 GPIO82/XA10 VSS VDD GPIO83/XA11 GPIO84/XA12 VDDIO VSS GPIO85/XA13 GPIO86/XA14 GPIO87/XA15 GPIO39/XA16 GPIO31/CANTXA/XA17133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 8988 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45GPIO48/ECAP5/XD31 TCK EMU1 EMU0 VDD3VFL VSS TEST2 TEST1 XRS TMS TRST TDO TDI GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO27/ECAP4/EQEP2S/MFSXB GPIO26/ECAP3/EQEP2I/MCLKXB VDDIO VSS GPIO25/ECAP2/EQEP2B/MDRB GPIO24/ECA